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CY7C67300
EZ-HostTM Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support
EZ-Host Features
* Single chip programmable USB dual-role (Host/Peripheral) controller with two configurable Serial Interface Engines (SIEs) and four USB ports * Support for USB On-The-Go (OTG) protocol * On-chip 48 MHz 16-bit processor with dynamically switchable clock speed * Configurable IO block supporting a variety of IO options or up to 32 bits of General Purpose IO (GPIO) * 4K x 16 internal masked ROM containing built in BIOS that supports a communication ready state with access to I2CTM EEPROM Interface, external ROM, UART, or USB * 8K x 16 internal RAM for code and data buffering * Extended memory interface port for external SRAM and ROM * 16-bit parallel Host Port Interface (HPI) with a DMA/mailbox data path for an external processor to directly access all of the on-chip memory and control on-chip SIEs * Fast serial port supports from 9600 baud to 2.0M baud * * * * * * SPI support in both master and slave On-chip 16-bit DMA/mailbox data path interface Supports 12 MHz external crystal or clock 3.3V operation Automotive AEC grade option (-40C to 85C) Package option--100-pin TQFP
Typical Applications
EZ-Host is a very powerful and flexible dual role USB controller that supports a wide variety of applications. It is primarily intended to enable host capability in applications such as: * Set top boxes * Printers * KVM switches * Kiosks * Automotive applications * Wireless access points
CY7C67300 Block Diagram
CY7C67300
nRESET
Control
Timer 0
Timer 1 UART I/F I2C EEPROM I/F
Watchdog
CY16 16-bit RISC CORE
Vbus, ID OTG D+,DUSB-A
HSS I/F PWM SPI I/F IDE I/F
SHARED INPUT/OUTPUT PINS
GPIO [31:0]
SIE1
Host/ Peripheral USB Ports D+,DUSB-B
D+,D-
USB-A
SIE2
D+,DUSB-B
4Kx16 ROM BIOS
8Kx16 RAM
HPI I/F
GPIO
X1 X2 PLL
Mobile Power Booster
External MEM I/F (SRAM/ROM)
SHARED INPUT/OUTPUT PINS
A[15:0] D[15:0]
CTRL[9:0]
Cypress Semiconductor Corporation Document #: 38-08015 Rev. *H
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised May 16, 2007
CY7C67300
Introduction
EZ-HostTM (CY7C67300) is Cypress Semiconductor's first full-speed, low cost multiport host/peripheral controller. EZ-Host is designed to easily interface to most high performance CPUs to add USB host functionality. EZ-Host has its own 16-bit RISC processor to act as a coprocessor or operate in standalone mode. EZ-Host also has a programmable IO interface block allowing a wide range of interface options.
Interrupts EZ-Host provides 128 interrupt vectors. The first 48 vectors are hardware interrupts and the following 80 vectors are software interrupts. General Timers and Watchdog Timer EZ-Host has two built in programmable timers and a Watchdog timer. All three timers can generate an interrupt to the EZ-Host. Power Management EZ-Host has one main power saving mode, Sleep. Sleep mode pauses all operations and provides the lowest power state.
Functional Overview
An overview of the processor core components are presented in this section. Processor Core EZ-Host has a general purpose 16-bit embedded RISC processor that runs at 48 MHz. Clocking EZ-Host requires a 12 MHz source for clocking. Either an external crystal or TTL level oscillator may be used. EZ-Host has an internal PLL that produces a 48 MHz internal clock from the 12 MHz source. Memory EZ-Host has a built in 4K x 16 masked ROM and an 8K x 16 internal RAM. The masked ROM contains the EZ-Host BIOS. The internal RAM can be used for program code or data.
Interface Descriptions
EZ-Host has a wide variety of interface options for connectivity. With several interface options available, EZ-Host can act as a seamless data transport between many different types of devices. See Table 1 and Table 2 on page 3 to understand how the interfaces share pins and which can coexist. Note that some interfaces have more then one possible port location selectable through the GPIO control register [0xC006]. General guidelines for interfaces are as follows: * HPI and IDE interfaces are mutually exclusive. * If 16-bit external memory is required, then HSS and SPI default locations must be used. * I2C EEPROM and OTG do not conflict with any interfaces.
Table 1.
Interface Options for GPIO Pins HPI IDE PWM HSS SPI UART I2C SCL/SDA SCL/SDA OTG
GPIO Pins GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24 GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11
OTGID TX RX PWM3 INT nRD nWR nCS A1 A0 IOREADY IOR IOW CS1 CS0 A2 A1 A0 D15 D14 D13 D12 D11 CTS[1]
PWM2 PWM1 PWM0
RTS[1] RXD[1] TXD[1]
D15 D14 D13 D12 D11
MOSI[1]
Note 1. Default interface location.
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Table 1.
Interface Options for GPIO Pins (continued) HPI D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IDE D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 PWM HSS SPI SCK[1] nSSI[1] MISO[1] UART I2C OTG
GPIO Pins GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
Table 2.
Interface Options for External Memory Bus Pins HPI IDE PWM HSS CTS[2] RTS[2] RXD[2] TXD[2] SPI UART I2C OTG
MEM Pins D15 D14 D13 D12 D11 D10 D9 D8 D[7:0] A[18:0] CONTROL USB Interface
MOSI[2] SCK[2] nSSI[2] MISO[2]
EZ-Host has two built in Host/Peripheral SIEs and four USB transceivers that meet the USB 2.0 specification requirements for full and low speed (high speed is not supported). In Host mode, EZ-Host supports four downstream ports, each support control, interrupt, bulk, and isochronous transfers. In Peripheral mode, EZ-Host supports one peripheral port with Table 3. OTG OTG + 2 Hosts OTG + 1 Host OTG + 1 Host OTG + 1 Peripheral OTG + 1 Peripheral 4 Hosts 3 Hosts 2 Hosts 1 Host
Note 2. Alternate interface location.
eight endpoints for each of the two SIEs. Endpoint 0 is dedicated as the control endpoint and only supports control transfers. Endpoints 1 though 7 support interrupt, bulk (up to 64 bytes/packet), or isochronous transfers (up to 1023 Bytes/packet size). EZ-Host also supports a combination of Host and Peripheral ports simultaneously as shown in Table 3.
USB Port Configuration Options Port Configurations Port 1A OTG OTG OTG OTG OTG OTG Host Port 1B - - - - - - Host Port 2A - Host Host - Peripheral - Host Port 2B - Host - Host - Peripheral Host
Any Combination of Ports Any Combination of Ports Any Port
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Table 3.
USB Port Configuration Options (continued) Port Configurations Port 1A Host Host Peripheral - Host Host - - Peripheral Peripheral - - Peripheral Peripheral - - Port 1B Host Host - Peripheral - - Host Host - - Peripheral Peripheral - - Peripheral Peripheral Any Port Request Protocol (SRP) and Host Negotiation Protocol (HNP). OTG is only supported on USB PORT 1A. OTG Features * Internal charge pump to supply and control VBUS * VBUS valid status (above 4.4V) * VBUS status for 2.4V< VBUS <0.8V * ID pin status * Switchable 2K ohm internal discharge resistor on VBUS * Switchable 500 ohm internal pull up resistor on VBUS * Individually switchable internal pull up and pull down resistors on the USB data lines OTG Pins USB Interface Pins Pin Name Pin Number 22 23 18 19 9 10 4 5 Table 5. OTG Interface Pins Pin Number 22 23 11 41 13 12 Port 2A Peripheral - Host Host Peripheral - - Peripheral Host - - Host Peripheral - - Peripheral Port 2B - Peripheral Host Host - Peripheral Peripheral - - Host Host - - Peripheral Peripheral -
2 Hosts + 1 Peripheral 2 Hosts + 1 Peripheral 2 Hosts + 1 Peripheral 2 Hosts + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 1 Host + 1 Peripheral 2 Peripherals 2 Peripherals 2 Peripherals 2 Peripherals 1 Peripheral
USB Features * USB 2.0-compliant for full and low speed * Up to four downstream USB host ports * Up to two upstream USB peripheral ports * Configurable endpoint buffers (pointer and length), must reside in internal RAM * Up to eight available peripheral endpoints (one control endpoint) * Supports control, interrupt, bulk, and isochronous transfers * Internal DMA channels for each endpoint * Internal pull up and pull down resistors * Internal series termination resistors on USB data lines USB Pins Table 4. DM1A DP1A DM1B DP1B DM2A DP2A DM2B DP2B OTG Interface EZ-Host has one USB port that is compatible with the USB On-The-Go supplement to the USB 2.0 specification. The USB OTG port has a various hardware features to support Session Document #: 38-08015 Rev. *H
Pin Name DM1A DP1A OTGVBUS OTGID CSwitchA CSwitchB External Memory Interface
EZ-Host provides a robust interface to a wide variety of external memory arrays. All available external memory array locations can contain either code or data. The CY16 RISC processor directly addresses a flat memory space from 0x0000 to 0xFFFF.
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External Memory Interface Features * Supports 8-bit or 16-bit SRAM or ROM * SRAM or ROM can be used for code or data space * Direct addressing of SRAM or ROM * Two external memory mapped page registers External Memory Access Strobes Access to external memory is sampled asynchronously on the rising edge of strobes with a minimum of one wait state cycle. Up to seven wait state cycles may be inserted for external memory access. Each additional wait state cycle stretches the external memory access time by 21 ns (you must be running in internal memory when changing wait states). An external memory device with 12 ns access time is necessary to support 48 MHz code execution. Page Registers EZ-Host allows extended data or program code to be stored in external SRAM, or ROM. The total size of extended memory can be up to 512K bytes. The CY16 processor can access extended memory via two address regions of 0x8000-0x9FFF and 0xA000-0xBFFF. The page register 0xC018 can be used to control the address region 0x8000-0x9FFF and the page register 0xC01A controls the address region of 0xA000-0xBFFF. Figure 1 illustrates that when the nXMEMSEL pin is asserted the upper CPU address pins are driven by the contents of the Page x registers. Figure 1. Page n Registers External Address Pins Logic
nXMEMSEL Pin 0000 + PC[14:0] PAGEx Register[5:0] + PC[12:0] 1 A[18:0] 0
Merge Mode Merge modes enabled through the External Memory Control register [0xC03A] allow combining of external memory regions in accordance with the following: * nXMEMSEL is active from 0x8000 to 0xBFFF * nXRAMSEL is active from 0x4000 to 0x7FFF when RAM Merge is disabled; nXRAMSEL is active from 0x4000 to 0xBFFF when RAM Merge is enabled * nXROMSEL is active from 0xC100 to 0xDFFF when ROM Merge is disabled; nXROMSEL is active from 0x8000 to 0xDFFF (excluding the 0xC000 to 0xC0FF area) when ROM Merge is enabled Program Memory Hole Description Code residing in the 0xC000-0xC0FF address space is not accessible by the CPU. DMA to External Memory Prohibited EZ-Host supports an internal DMA engine to rapidly move data between different functional blocks within the chip. This DMA engine is used for SIE1, SIE2, HPI, SPI, HSS, and IDE but it can only transfer data between the specified block and internal RAM or ROM. Setting up the DMA engine to transfer to or from an external memory space might result in internal RAM data corruption because the hardware (for example, HSS/HPI/SIE1/SIE2/IDE) does not explicitly check the address range. For example, setting up a DMA transfer to external address 0x8000 might result in a DMA transfer into address 0x0000. External Memory Related Resource Considerations: * By default A[18:15] are not available for general addressing and are driven high on power up. The Upper Address Enable register must be written appropriately to enable A[18:15] for general addressing purposes. * 47K ohm external pull up on pin A15 for 12 MHz crystal operation. * During the 3 ms BIOS boot procedure the CPU external memory bus is active. * ROM boot load value 0xC3B6 located at 0xC100. * HPI, HSS, SPI, SIE1, SIE2, and IDE cannot DMA to external memory arrays. * Page 1 banking is always enabled and is in effect from 0x8000 to 0x9FFF. * Page 2 banking is always enabled and is in effect from 0xA000 to 0xBFFF. * CPU memory bus strobes may wiggle when chip selects are inactive.
Where: x = 1 or 2 PC = Program Counter A = CPU Address Bus Note: PAGE 1 Register Active Range = 8000h to 9FFFh PAGE 2 Register Active Range = A000h to BFFFh nXMEMSEL Pin Active Range = 8000h to BFFFh
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External Memory Interface Pins Table 6. Table 6. External Memory Interface Pins Pin Name nWR nRD nXMEMSEL (optional nCS) nXROMSEL (ROM nCS) nXRAMSEL (RAM nCS) A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 nBEL/A0 nBEH D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 Pin Number 64 62 34 35 36 96 95 97 38 33 32 31 30 27 25 24 20 17 8 7 3 2 1 99 98 67 68 69 70 71 72 73 74 76 77 78 79
A[18:1] D[15:0] nXMEMSEL nBEL nBEH nWR nRD A[17:0] D[15:0] CE BLE BHE WE OE
A[15:0] D[7:0] nXRAMSEL nWR nRD A[15:0] D[7:0] CE WE OE
External Memory Interface Pins (continued) Pin Name D3 D2 D1 D0 Pin Number 80 81 82 83
External Memory Interface Block Diagrams Figure 2 illustrates how to connect a 64k x 8 memory array (SRAM/ROM) to the EZ-Host external memory interface. Figure 2. Interfacing to 64k x 8 Memory Array
Interfacing to 64K x 8 External Memory Array
EZ-Host CY7C67300 External Memory Array 64K x 8
Figure 3 illustrates the interface for connecting a 16-bit ROM or 16-bit RAM to the EZ-Host external memory interface. In 16-bit mode, up to 256K words of external ROM or RAM are supported. Note that the address lines do not map directly. Figure 3. Interfacing up to 256k x 16 for External Code/Data
Up to 256k x 16 External Code/Data (Page Mode)
EZ-Host CY7C67300 External Memory Array Up to 256k x 16
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Figure 4 illustrates the interface for connecting an 8-bit ROM or 8-bit RAM to the EZ-Host external memory interface. In 8-bit mode, up to 512K bytes of external ROM or RAM are supported.
Figure 4. Interfacing up to 512k x 8 for External Code/Data
I2C EEPROM Interface
Up to 512k x 8 External Code/Data (Page Mode)
EZ-Host CY7C67300 External Memory Array Up to 512k x8
EZ-Host provides a master-only I2C interface for external serial EEPROMs. The serial EEPROM can be used to store application specific code and data. Use the I2C interface for loading code out of EEPROM, it is not a general I2C interface. The I2C EEPROM interface is a BIOS implementation and is exposed through GPIO pins. Refer to the BIOS documentation for additional details on this interface.
I2C EEPROM Features * Supports EEPROMs up to 64 KB (512K bit) * Auto-detection of EEPROM size I2C EEPROM Pins Table 8. I2C EEPROM Interface Pins Pin Number SMALL EEPROM GPIO Number
A[18:0] D[7:0] nXMEMSEL nWR nRD
A[18:0] D[7:0] CE WE OE
Pin Name
SCK SDA
General Purpose IO Interface (GPIO)
EZ-Host has up to 32 GPIO signals available. Several other optional interfaces use GPIO pins as well and may reduce the overall number of available GPIOs.
GPIO Description
SCK SDA
39 40 LARGE EEPROM 40 39
GPIO31 GPIO30 GPIO30 GPIO31
Serial Peripheral Interface
All Inputs are sampled asynchronously with state changes occurring at a rate of up to two 48 MHz clock cycles. GPIO pins are latched directly into registers, a single flip-flop.
Unused Pin Descriptions
EZ-Host provides a SPI interface for added connectivity. EZ-Host may be configured as either an SPI master or SPI slave. The SPI interface can be exposed through GPIO pins or the External Memory port.
SPI Features * Master or slave mode operation * DMA block transfer and PIO byte transfer modes * Full duplex or half duplex data communication * 8-byte receive FIFO and 8-byte transmit FIFO * Selectable master SPI clock rates from 250 kHz to 12 MHz * Selectable master SPI clock phase and polarity * Slave SPI signaling synchronization and filtering * Slave SPI clock rates up to 2 MHz * Maskable interrupts for block and byte transfer modes * Individual bit transfer for non-byte aligned serial communication in PIO mode * Programmable delay timing for the active/inactive master SPI clock * Auto or manual control for master mode slave select signal * Complete access to internal memory
Ensure to tristate unused USB pins with the D+ line pulled high through the internal pull up resistor and the D- line pulled low through the internal pull down resistor. Configure unused GPIO pins as outputs so they are driven low.
UART Interface
EZ-Host has a built in UART interface. The UART interface supports data rates from 900 to 115.2K baud. It can be used as a development port or for other interface requirements. The UART interface is exposed through GPIO pins.
UART Features * Supports baud rates of 900 to 115.2K * 8-N-1 UART Pins. Table 7. UART Interface Pins Pin Name Pin Number
TX RX
42 43
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SPI Pins
HSS Pins
The SPI port has a few different pin location options as shown in Table 9. The port location is selectable via the GPIO control register [0xC006].
Table 9. SPI Interface Pins Pin Name Default Location Pin Number
The HSS port has a few different pin location options as shown in Table 10. The port location is selectable via the GPIO control register [0xC006].
Table 10. HSS Interface Pins Pin Name Default Location Pin Number
nSSI SCK MOSI MISO
Alternate Location
56 or 65 61 60 66 73 72 71 74
CTS RTS RXD TXD
Alternate Location
44 53 54 55 67 68 69 70
nSSI SCK MOSI MISO
High-Speed Serial Interface
CTS RTS RXD TXD
Programmable Pulse/PWM Interface
EZ-Host provides an HSS interface. The HSS interface is a programmable serial connection with baud rate from 9600 baud to 2.0M baud. The HSS interface supports both byte and block mode operations and also hardware and software handshaking. Complete control of EZ-Host can be accomplished through this interface via an extensible API and communication protocol. The HSS interface can be exposed through GPIO pins or the External Memory port.
HSS Features * 8 bits, no parity code * Programmable baud rate from 9600 baud to 2M baud * Selectable 1- or 2-stop bit on transmit * Programmable inter-character gap timing for Block Transmit * 8-byte receive FIFO * Glitch filter on receive * Block mode transfer directly to/from EZ-Host internal memory (DMA transfer) * Selectable CTS/RTS hardware signal handshake protocol * Selectable XON/XOFF software handshake protocol * Programmable Receive interrupt, Block Transfer Done interrupts * Complete access to internal memory
EZ-Host has four built in PWM output channels. Each channel provides a programmable timing generator sequence that can be used to interface to various image sensors or other applications. The PWM interface is exposed through GPIO pins.
Programmable Pulse/PWM Features * Four independent programmable waveform generators * Programmable predefined frequencies ranging from 5.90 KHz to 48 MHz * Configurable polarity * Continuous and one-shot mode available Programmable Pulse/PWM Pins. Table 11. PWM Interface Pins Pin Name Pin Number
PWM3 PWM2 PWM1 PWM0
Host Port Interface
44 53 54 55
EZ-Host has an HPI interface. The HPI interface provides DMA access to the EZ-Host internal memory by an external host, plus a bidirectional mailbox register for supporting high level communication protocols. This port is designed to be the primary high-speed connection to a host processor. Complete control of EZ-Host can be accomplished through this interface via an extensible API and communication protocol. Other than
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HPI Features * 16-bit data bus interface * 16 MB/s throughput * Auto-increment of address pointer for fast block mode transfers * Direct memory access (DMA) to internal memory * Bidirectional Mailbox register * Byte swapping * Complete access to internal memory * Complete control of SIEs through HPI * Dedicated HPI status register HPI Pins Table 12. HPI Interface Pins[3, 4] Pin Name Pin Number
The two HPI address pins are used to address one of four possible HPI port registers as shown in Table 13.
Table 13. HPI Addressing HPI A[1:0] A1 A0
HPI Data HPI Mailbox HPI Address HPI Status
IDE Interface
0 0 1 1
0 1 0 1
INT nRD nWR nCS A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
46 47 48 49 50 52 56 57 58 59 60 61 65 66 86 87 89 90 91 92 93 94
EZ-Host has an IDE interface. The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment-4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. There is no need for firmware to use programmable wait states. The CPU read/write cycle is automatically extended as needed for direct CPU to IDE read/write accesses. The EZ-Host IDE interface also has a BLOCK transfer mode that allows EZ-Host to read/write large blocks of data to/from the IDE data register and move it to/from the EZ-Host on-chip memory directly without intervention of the CPU. The IDE interface is exposed through GPIO pins. Table 14 on page 10 lists the achieved throughput for maximum block mode data transfer rate (with IDE_IORDY true) for the various IDE PIO modes.
Notes 3. HPI_INT is for the Outgoing Mailbox interrupt. 4. HPI strobes are negative logic sampled on rising edge.
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Table 14. IDE Throughput ATA/ATAPI-4 Min. Cycle Time PIO Mode 0 600 ns PIO Mode 1 383 ns PIO Mode 2 240 PIO Mode 3 180 ns PIO Mode 4 120 ns T = System clock period = 1/48 MHz. Mode Actual Min. Cycle Time 30T = 625 ns 20T = 416.7 ns 13T = 270.8 ns 10T = 208.3 ns 8T = 166.7 ns ATA/ATPI-4 Max. Transfer Rate 3.33 MB/s 5.22 MB/s 8.33 MB/s 11.11 MB/s 16.67 MB/s Actual Max. Transfer Rate 3.2 MB/s 4.8 MB/s 7.38 MB/s 9.6 MB/s 12.0 MB/s
IDE Features * Programmable IO mode 0-4 * Block mode transfers * Direct memory access to/from internal memory through the IDE data register IDE Pins Table 15. IDE Interface Pins Pin Name Pin Number
Charge Pump Interface
VBUS for the USB OTG port can be produced by EZ-Host using its built in charge pump and some external components. Ensure the circuit connections look similar to the following diagram. Figure 5. Charge Pump
D1
CSWITCHA CY7C67300
D2
IORDY IOR IOW CS1 CS0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
46 47 48 50 52 53 54 55 56 57 58 59 60 61 65 66 86 87 89 90 91 92 93 94
CSWITCHB
C1
OTGVBUS
VBUS C2
Component details: * D1 and D2: Schottky diodes with a current rating greater than 60 mA * C1: Ceramic capacitor with a capacitance of 0.1 F * C2: Make capacitor value no more that 6.5 F since that is the maximum capacitance allowed by the USB OTG specifications for a dual role device. The minimum value of C2 is 1 F. There are no restrictions on the type of capacitor for C2. If the VBUS charge pump circuit is not to be used, CSWITCHA, CSWITCHB, and OTGVBUS can be left unconnected.
Charge Pump Features * Meets OTG Supplement Requirements, see Table 54, DC Characteristics: Charge Pump on page 84 for details. Charge Pump Pins Table 16. Charge Pump Interface Pins Pin Name Pin Number
OTGVBUS CSwitchA CSwitchB
11 13 12
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Booster Interface
Booster Pins Table 17. Charge Pump Interface Pins Pin Name Pin Number
EZ-Host has an on chip power booster circuit for use with power supplies that range between 2.7V and 3.6V. The booster circuit boosts the power to 3.3V nominal to supply power for the entire chip. The booster circuit requires an external inductor, diode, and capacitor. During power down mode, the circuit is disabled to save power. Figure 6 shows how to connect the booster circuit.
Figure 6. Power Supply Connection With Booster
BOOSTVcc VSWITCH
Crystal Interface
16 14
BOOSTVcc L1 2.7V to 3.6V Power Supply
The recommended crystal circuit to be used with EZ-Host is shown in Figure 8 If an oscillator is used instead of a crystal circuit, connect it to XTALIN and leave XTALOUT unconnected. For further information about the crystal requirements, see Table 52, Crystal Requirements on page 83. Noted that the CLKSEL pin (pin 38) is sampled after reset to determine what crystal or clock source frequency is used. For normal operation, 12 MHz is required so the CLKSEL pin must have a 47K ohm pull up resistor to VCC..
Figure 8. Crystal Interface
VSWITCH D1 3.3V
XTALIN
VCC AVCC
C1
CY7C67300
Y1
Component details: * L1: Inductor with inductance of 10 H and a current rating of at least 250 mA * D1: Schottky diode with a current rating of at least 250 mA * C1: Tantalum or ceramic capacitor with a capacitance of at least 2.2 F Figure 7 shows how to connect the power supply when the booster circuit is not being used.
Figure 7. Power Supply Connection Without Booster
XTALOUT C1 = 22 pF
12MHz Parallel Resonant Fundamental Mode 500uW 20-33pf 5%
C2 = 22 pF
Crystal Pins Table 18. Crystal Pins
BOOSTVcc 3.0V to 3.6V Power Supply
Pin Name
Pin Number
XTALIN XTALOUT
29 28
VSWITCH
VCC AVCC
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Boot Configuration Interface
Coprocessor Mode
EZ-Host can boot into any one of four modes. The mode it boots into is determined by the TTL voltage level of GPIO[31:30] at the time nRESET is deasserted. Table 19 shows the different boot pin combinations possible. After a reset pin event occurs, the BIOS bootup procedure executes for up to 3 ms. GPIO[31:30] are sampled by the BIOS during bootup only. After bootup these pins are available to the application as GPIOs.
Table 19. Boot Configuration Interface GPIO31 (Pin 39) GPIO30 (Pin 40) Boot Mode
EZ-Host can act as a coprocessor to an external host processor. In this mode, an external host processor drives EZ-Host and is the main processor rather then EZ-Host's own 16-bit internal CPU. An external host processor may interface to EZ-Host through one of the following three interfaces in coprocessor mode: * HPI mode, a 16 bit parallel interface with up to 16 MB transfer rate * HSS mode, a serial interface with up to 2M baud transfer rate * SPI mode, a serial interface with up to 2 Mb/s transfer rate At bootup GPIO[31:30] determine which of these three interfaces are used for coprocessor mode. See Table 19 for details. Bootloading begins from the selected interface after POR + 3 ms of BIOS bootup.
Standalone Mode
0 0 1 1
0 1 0 1
Host Port Interface (HPI) High-Speed Serial (HSS) Serial Peripheral Interface (SPI, slave mode) I2C EEPROM (Standalone Mode)
Ensure that GPIO[31:30] is pulled high or low as needed using resistors tied to VCC or GND with resistor values between 5K ohms and 15K ohms. Do not tie GPIO[31:30] directly to VCC or GND. Note that in standalone mode, the pull ups on those two pins are used for the serial I2C EEPROM (if implemented). Make sure that the resistors used for these pull ups conform to the serial EEPROM manufacturer's requirements. If any mode other then standalone is chosen, EZ-Host is in coprocessor mode. The device powers up with the appropriate communication interface enabled according to its boot pins and waits idle until a coprocessor communicates with it. See the BIOS documentation for greater detail of the boot process.
Operational Modes
In standalone mode, there is no external processor connected to EZ-Host. Instead, EZ-Host's own internal 16-bit CPU is the main processor and firmware is typically downloaded from an EEPROM. Optionally, firmware may also be downloaded via USB. See Table 19 for booting into standalone mode. After booting into standalone mode (GPIO[31:30] = `11'), the following pins are affected: * GPIO[31:30] are configured as output pins to examine the EEPROM contents * GPIO[28:27] are enabled for debug UART mode * GPIO[29] is configured for as OTGID for OTG applications on PORT1A -- If OTGID is logic 1 then PORT1A (OTG) is configured as a USB peripheral -- If OTGID is logic 0 then PORT1A (OTG) is configured as a USB host * Ports 1B, 2A, and 2B default as USB peripheral ports * All other pins remain INPUT pins.
The operational modes are discussed in the following sections.
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Minimum Hardware Requirements for Standalone Mode - Peripheral Only Figure 9. Minimum Standalone Hardware Configuration - Peripheral Only
EZ-Host CY7C67300 VReg VBus D+ DGND SHIELD Bootstrap Options Vcc Vcc Pin 38 10k 10k GPIO[30] GPIO[31] SCL* SDA* Int. 16k x8 Code / Data VCC A0 A1 A2 GND Up to 64k x8 EEPROM VCC WP SCL SDA GND, AGND, BoostGND *Bootloading begins after POR + 3ms BIOS bootup *GPIO[31:30] Up to 2k x8 >2k x8 to 64k x8 31 30 SCL SDA SDA SCL Reserved XIN
12MHz 22pf
VCC, AVCC, BoostVCC DPlus DMinus
nRESET
Reset Logic
Standard-B or Mini-B
VCC
47Kohm
Bootloading Firmware
XOUT
22pf
* Parallel Resonant Fundamental Mode 500uW 20-33pf 5%
Power Savings and Reset Description
This sections describes the different modes for resetting the chip and ways to save power.
Power Saving Mode Description
Sleep
EZ-Host has one main power saving mode, Sleep. For detailed information about Sleep mode, see the Sleep section that follows. Sleep mode is used for USB applications to support USB suspend and non USB applications as the main chip power down mode. In addition, EZ-Host is capable of slowing down the CPU clock speed through the CPU Speed register [0xC008] without affecting other peripheral timing. Reducing the CPU clock speed from 48 MHz to 24 MHz reduces the overall current draw by around 8 mA while reducing it from 48 MHz to 3 MHz reduces the overall current draw by approximately 15 mA.
Sleep mode is the main chip power down mode and is also used for USB suspend. Sleep mode is entered by setting the Sleep Enable (bit 1) of the Power control register [0xC00A]. During Sleep mode (USB Suspend) the following events and states are true: * GPIO pins maintain their configuration during sleep (in suspend) * External Memory address pins are driven low * XTALOUT is turned off * Internal PLL is turned off * Ensure that firmware disables the charge pump (OTG Control register [0xC098]) thereby causing OTGVBUS to drop below 0.2V. Otherwise OTGVBUS only drops to VCC - (2 schottky diode drops). * Booster circuit is turned off * USB transceivers is turned off * CPU goes into suspend mode until a programmable wakeup event Page 13 of 98
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External (Remote) Wakeup Source
There are several possible events available to wake EZ-Host from Sleep mode as shown in Table 20. These may also be used as remote wakeup options for USB applications. See the Power Control Register [0xC00A] [R/W] on page 19 for details. Upon wakeup, code begins executing within 200 s, the time it takes the PLL to stabilize.
Table 20. Wakeup Sources[5, 6] Wakeup Source (if enabled) Event
contained within this 64K space. This memory space is byte addressable. Figure 10 on page 15 shows the various memory region address locations.
Internal Memory
USB Resume OTGVBUS OTGID HPI HSS SPI IRQ1 (GPIO 25) IRQ0 (GPIO 24)
Power-On-Reset Description
D+/D- Signaling Level Any Edge Read Read Read Any Edge Any Edge
Of the internal memory, 15K bytes are allocated for user's program and data. The lower memory space from 0x0000 to 0x04A2 is reserved for interrupt vectors, general purpose registers, USB control registers, stack, and other BIOS variables. The upper internal memory space contains EZ-Host control registers from 0xC000 to 0xC0FF and the BIOS ROM itself from 0xE000 to 0xFFFF. For more information about the reserved lower memory or the BIOS ROM, refer to the Programmer's documentation and/or the BIOS documentation. During development with the EZ-Host toolset, leave the lower area of user's space (0x04A4 to 0x1000) available to load the GDB stub. The GDB stub is required to allow the toolset debug access into EZ-Host. The chip select pins are not active during accesses to internal memory.
External Memory
The length of the power-on-reset event can be defined by (VCC ramp to valid) + (Crystal startup). A typical application might use a 12 ms power-on-reset event = ~7 ms + ~5 ms, respectively.
Reset Pin
Up to 32 KB of external memory from 0x4000 - 0xBFFF is available via one chip select line (nXRAMSEL) with RAM Merge enabled (BIOS default). Additionally, another 8 KB region from 0xC100 - 0xDFFF is available via a second chip select line (nXROMSEL) giving 40 KB of total available external memory. Together with the internal 15 KB, this gives a total of either ~48 KB (one chip select) or ~56 KB (two chip selects) of available memory for either code or data. Note that the memory map and pin names (nXRAMSEL/nXROMSEL) define specific memory regions for RAM vs. ROM. This allows the BIOS to look in the upper external memory space at 0xC100 for SCAN vectors (enabling code to be loaded/executed from ROM). If no SCAN vectors are required in the design (external memory is used exclusively for data), then all external memory regions can be used for RAM. Similarly, the external memory can be used exclusively for code space (ROM). If more external memory is required, EZ-Host has enough address lines to support up to 512 KB. However, this requires complex code banking/paging schemes via the Extended Page registers. For further information about setting up the external memory, see the External Memory Interface on page 5.
The Reset pin is active low and requires a minimum pulse duration of sixteen 12 MHz clock cycles (1.3 s). A reset event restores all registers to their default POR settings. Code execution then begins 200 s later at 0xFF00 with an immediate jump to 0xE000, the start of BIOS. Refer to BIOS documentation for additional details.
USB Reset
A USB Reset affects registers 0xC090 and 0xC0B0, all other registers remain unchanged.
Memory Map
The memory map is discussed in the following sections.
Mapping
The total memory space directly addressable by the CY16 processor is 64K (0x0000-0xFFFF). Program, data, and IO are
Notes 5. Read data is discarded (dummy data). 6. HPI_INT asserts on a USB Resume.
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Figure 10. Memory Map
Internal Memory
HW INT's 0x0000 - 0x00FF SW INT's 0x0100 - 0x011F 0x0120 - 0x013F 0x0140 - 0x0148 0x014A - 0x01FF 0x0200 - 0x02FF 0x0300 - 0x030F 0x0310 - 0x03FF 0x0400 - 0x04A2 0x04A4 - 0x3FFF Primary Registers Swap Registers HPI Int / Mailbox LCP Variables USB Registers Slave Setup Packet BIOS Stack USB Slave & OTG USER SPACE ~15K
External Memory
0x4000 - 0x7FFF USER SPACE 16K
0x8000 - 0x9FFF
Extended Page 1 USER SPACE 01 Up to 64 8K Banks
Bank Selected by 0xC018 Bank Selected by 0xC01A
0xA000 - 0xBFFF
Extended Page 2 USER SPACE 01 Up to 64 8K Banks
0xC000 - 0xC0FF
Control Registers 0xC100 - 0xDFFF USER SPACE ~8K
0xE000 - 0xFFFF
BIOS
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Registers
Some registers have different functions for a read vs. a write access or USB host vs. USB device mode. Therefore, registers of this type have multiple definitions for the same address. The default register values listed in this data sheet may be altered to some other value during the BIOS initialization. Refer to the BIOS documentation for register initialization information.
Processor Control Registers
Table 21. Processor Control Registers Register Name Address R/W
CPU Flags Register Register Bank Register Hardware Revision Register CPU Speed Register Power Control Register Interrupt Enable Register Breakpoint Register USB Diagnostic Register Memory Diagnostic Register
0xC000 0xC002 0xC004 0xC008 0xC00A 0xC00E 0xC014 0xC03C 0xC03E
R R/W R R/W R/W R/W R/W W W
There are nine registers dedicated to general processor control. Each of these registers are covered in this section and are summarized in Table 21.
CPU Flags Register [0xC000] [R] Figure 11. CPU Flags Register
Bit # Field Read/Write Default Bit # 0 7 0 6 ...Reserved Field Read/Write Default 0 0 0 0 5 0 4 Global Interrupt Enable R X 15 14 13 12 Reserved... 0 3 Negative Flag R X 0 2 Overflow Flag R X 0 1 Carry Flag R X 0 0 Zero Flag R X 11 10 9 8
Register Description
The CPU Flags register is a read only register that gives processor flags status.
Global Interrupt Enable (Bit 4)
result was either larger than the destination operand size (for addition) or smaller than the destination operand must allow for subtraction.
1: Overflow occurred 0: Overflow did not occur Carry Flag (Bit 1)
The Global Interrupt Enable bit indicates if the Global Interrupts are enabled.
1: Enabled 0: Disabled Negative Flag (Bit 3)
The Carry Flag bit indicates if an arithmetic operation resulted in a Carry for addition, or Borrow for subtraction.
1: Carry/Borrow occurred 0: Carry/Borrow did not occur Zero Flag (Bit 0)
The Negative Flag bit indicates if an arithmetic operation results in a negative answer.
1: MS result bit is `1' 0: MS result bit is not `1' Overflow Flag (Bit 2)
The Zero Flag bit indicates if an instruction execution resulted in a `0'.
1: Zero occurred 0: Zero did not occur
The Overflow Flag bit indicates if an overflow condition occurred. An overflow condition can occur if an arithmetic
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Bank Register [0xC002] [R/W] Figure 12. Bank Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 7 R/W 0 6 ...Address R/W 0 R/W 0 X X R/W 0 5 R/W 0 4 15 14 13 12 Address... R/W 0 3 R/W 0 2 Reserved X X X R/W 0 1 R/W 1 0 11 10 9 8
Register Description
The Bank register maps registers R0-R15 into RAM. The eleven MSBs of this register are used as a base address for registers R0-R15. A register address is automatically generated by: 1. Shifting the four LSBs of the register address left by 1. 2. ORing the four shifted bits of the register address with the twelve MSBs of the Bank register. 3. Forcing the LSB to zero. For example, if the Bank register is left at its default value of 0x0100, and R2 is read, then the physical address 0x0102 is read. Refer to Table 22 for details.
Table 22. Bank Register Example Register Hex Value Binary Value
Bank R14 RAM Location
Address (Bits [15:4])
0x0100 0x000E << 1 = 0x001C 0x011C
0000 0001 0000 0000 0000 0000 0001 1100 0000 0001 0001 1100
The Address field is used as a base address for all register addresses to start from.
Reserved
Write all reserved bits with '0'.
Hardware Revision Register [0xC004] [R] Figure 13. Revision Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R X R X R X R X R X 7 R X 6 R X 5 R X 4 ...Revision R X R X R X R X 15 14 13 12 Revision... R X 3 R X 2 R X 1 R X 0 11 10 9 8
Register Description
The Hardware Revision register is a read only register that indicates the silicon revision number. The first silicon revision is represented by 0x0101. This number is increased by one for each new silicon revision.
Revision (Bits [15:0])
The Revision field contains the silicon revision number.
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CPU Speed Register [0xC008] [R/W] Figure 14. CPU Speed Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 0 7 0 6 ...Reserved 0 0 R/W 1 1 0 5 0 4 15 14 13 12 Reserved... 0 3 0 2 CPU Speed R/W R/W 1 R/W 1 0 1 0 0 11 10 9 8
Register Description
The CPU Speed register allows the processor to operate at a user selected speed. This register only affects the CPU, all other peripheral timing is still based on the 48 MHz system clock (unless otherwise noted).
CPU Speed (Bits[3:0])
The CPU Speed field is a divisor that selects the operating speed of the processor as defined in Table 23.
Table 23. CPU Speed Definition CPU Speed [3:0] Processor Speed
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Reserved
48 MHz/1 48 MHz/2 48 MHz/3 48 MHz/4 48 MHz/5 48 MHz/6 48 MHz/7 48 MHz/8 48 MHz/9 48 MHz/10 48 MHz/11 48 MHz/12 48 MHz/13 48 MHz/14 48 MHz/15 48 MHz/16
Write all reserved bits with '0'.
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Power Control Register [0xC00A] [R/W] Figure 15. Power Control Register
Bit # 15 Host/Device 2B Wake Enable R/W 0 7 HPI Wake Enable R/W 0 0 14 Host/Device 2A Wake Enable R/W 0 6 Reserved 13 Host/Device 1B Wake Enable R/W 0 5 12 Host/Device 1A Wake Enable R/W 0 4 GPI Wake Enable 0 R/W 0 11 OTG Wake Enable R/W 0 3 Reserved 10 Reserved 9 HSS Wake Enable R/W 0 1 Sleep Enable R/W 0 8 SPI Wake Enable R/W 0 0 Halt Enable R/W 0
Field Read/Write Default Bit #
0 2 Boost 3V OK R 0
Field Read/Write Default
0
Register Description
OTG Wake Enable (Bit 11)
The Power Control register controls the power down and wakeup options. Either the sleep mode or the halt mode options can be selected. All other writable bits in this register can be used as a wakeup source while in sleep mode.
Host/Device 2B Wake Enable (Bit 15)
The OTG Wake Enable bit enables or disables a wakeup condition to occur on either an OTG VBUS_Valid or OTG ID transition (IRQ20).
1: Enable wakeup on OTG VBUS valid or OTG ID transition 0: Disable wakeup on OTG VBUS valid or OTG ID transition HSS Wake Enable (Bit 9)
The Host/Device 2B Wake Enable bit enables or disables a wakeup condition to occur on a Host/Device 2B transition. This wakeup from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wakeup on Host/Device 2B transition 0: Disable wakeup on Host/Device 2B transition Host/Device 2A Wake Enable (Bit 14)
The HSS Wake Enable bit enables or disables a wakeup condition to occur on an HSS Rx serial input transition. The processor may take several hundreds of microseconds before being operational after wakeup. Therefore, the incoming data byte that causes the wakeup is discarded.
1: Enable wakeup on HSS Rx serial input transition 0: Disable wakeup on HSS Rx serial input transition SPI Wake Enable (Bit 8)
The Host/Device 2A Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 2A transition. This wakeup from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wakeup on Host/Device 2A transition 0: Disable wakeup on Host/Device 2A transition Host/Device 1B Wake Enable (Bit 13)
The SPI Wake Enable bit enables or disables a wakeup condition to occur on a falling SPI_nSS input transition. The processor may take several hundreds of microseconds before being operational after wakeup. Therefore, the incoming data byte that causes the wakeup is discarded.
1: Enable wakeup on falling SPI nSS input transition 0: Disable SPI_nSS interrupt HPI Wake Enable (Bit 7)
The Host/Device 1B Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 1B transition. This wakeup from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wakeup on Host/Device 1B transition 0: Disable wakeup on Host/Device 1B transition Host/Device 1A Wake Enable (Bit 12)
The HPI Wake Enable bit enables or disables a wakeup condition to occur on an HPI interface read.
1: Enable wakeup on HPI interface read 0: Disable wakeup on HPI interface read GPI Wake Enable (Bit 4)
The Host/Device 1A Wake Enable bit enables or disables a wakeup condition to occur on an Host/Device 1A transition. This wakeup from the SIE port does not cause an interrupt to the on-chip CPU.
1: Enable wakeup on Host/Device 1A transition 0: Disable wakeup on Host/Device 1A transition
The GPI Wake Enable bit enables or disables a wakeup condition to occur on a GPIO(25:24) transition.
1: Enable wakeup on GPIO(25:24) transition 0: Disable wakeup on GPIO(25:24) transition
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Boost 3V OK (Bit 2)
Halt Enable (Bit 0)
The Boost 3V OK bit is a read only bit that returns the status of the OTG Boost circuit.
1: Boost circuit not ok and internal voltage rails are below 3.0V 0: Boost circuit ok and internal voltage rails are at or above 3.0V Sleep Enable (Bit 1)
Setting this bit to `1' immediately initiates HALT mode. While in HALT mode, only the CPU is stopped. The internal clock still runs and all peripherals still operate, including the USB engines. The power saving using HALT in most cases is minimal, but in applications that are very CPU intensive the incremental savings may provide some benefit. The HALT state is exited when any enabled interrupt is triggered. Upon exiting the HALT state, one or two instructions immediately following the HALT instruction may be executed before the waking interrupt is serviced (you may want to follow the HALT instruction with two NOPs).
1: Enable Halt mode 0: No function Reserved
Setting this bit to `1' immediately initiates SLEEP mode. While in SLEEP mode, the entire chip is paused, achieving the lowest standby power state. All operations are paused, the internal clock is stopped, the booster circuit and OTG VBUS charge pump are all powered down, and the USB transceivers are powered down. All counters and timers are paused but retain their values; enabled PWM outputs freeze in their current states. SLEEP mode exits by any activity selected in this register. When SLEEP mode ends, instruction execution resumes within 0.5 ms.
1: Enable Sleep mode 0: No function
Write all reserved bits with '0'.
Interrupt Enable Register [0xC00E] [R/W] Figure 16. Interrupt Enable Register
Bit # 15 14 Reserved Field Read/Write Default Bit # 0 7 HSS Interrupt Enable R/W 0 0 6 In Mailbox Interrupt Enable R/W 0 0 5 Out Mailbox Interrupt Enable R/W 0 13 12 OTG Interrupt Enable R/W 0 4 Reserved 11 SPI Interrupt Enable R/W 0 3 UART Interrupt Enable R/W 0 10 Reserved 9 8 Host/Device 2 Host/Device 1 Interrupt Interrupt Enable Enable R/W 0 1 Timer 1 Interrupt Enable R/W 0 R/W 0 0 Timer 0 Interrupt Enable R/W 0
0 2 GPIO Interrupt Enable R/W 0
Field Read/Write Default
1
Register Description
Host/Device 2 Interrupt Enable (Bit 9)
The Interrupt Enable register allows control of the hardware interrupt vectors.
OTG Interrupt Enable (Bit 12)
The OTG Interrupt Enable bit enables or disables the OTG ID/OTG4.4V Valid hardware interrupt.
1: Enable OTG interrupt 0: Disable OTG interrupt SPI Interrupt Enable (Bit 11)
The Host/Device 2 Interrupt Enable bit enables or disables all of the following Host/Device 2 hardware interrupts: Host 2 USB Done, Host 2 USB SOF/EOP, Host 2 Wakeup/Insert/Remove, Device 2 Reset, Device 2 SOF/EOP or WakeUp from USB, Device 2 Endpoint n.
1: Enable Host 2 and Device 2 interrupt 0: Disable Host 2 and Device 2 interrupt Host/Device 1 Interrupt Enable (Bit 8)
The SPI Interrupt Enable bit enables or disables the following three SPI hardware interrupts: SPI TX, SPI RX, and SPI DMA Block Done.
1: Enable SPI interrupt 0: Disable SPI interrupt
The Host/Device 1 Interrupt Enable bit enables or disables all of the following Host/Device 1 hardware interrupts: Host 1 USB Done, Host 1 USB SOF/EOP, Host 1 Wakeup/Insert/Remove, Device 1 Reset, Device 1 SOF/EOP or WakeUp from USB, Device 1Endpoint n.
1: Enable Host 1 and Device 1 interrupt 0: Disable Host 1 and Device 1 interrupt
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HSS Interrupt Enable (Bit 7)
GPIO Interrupt Enable (Bit 2)
The HSS Interrupt Enable bit enables or disables the following High-speed Serial Interface hardware interrupts: HSS Block Done and HSS RX Full.
1: Enable HSS interrupt 0: Disable HSS interrupt In Mailbox Interrupt Enable (Bit 6)
The GPIO Interrupt Enable bit enables or disables the General Purpose IO pins interrupt (see the GPIO Control Register [0xC006] [R/W] on page 50). When the GPIO bit is reset, all pending GPIO interrupts are also cleared
1: Enable GPIO interrupt 0: Disable GPIO interrupt Timer 1 Interrupt Enable (Bit 1)
The In Mailbox Interrupt Enable bit enables or disables the HPI: Incoming Mailbox hardware interrupt.
1: Enable MBXI interrupt 0: Disable MBXI interrupt Out Mailbox Interrupt Enable (Bit 5)
The Timer 1 Interrupt Enable bit enables or disables the TImer1 Interrupt Enable. When this bit is reset, all pending Timer 1 interrupts are cleared.
1: Enable TM1 interrupt 0: Disable TM1 interrupt Timer 0 Interrupt Enable (Bit 0)
The Out Mailbox Interrupt Enable bit enables or disables the HPI: Outgoing Mailbox hardware interrupt.
1: Enable MBXO interrupt 0: Disable MBXO interrupt UART Interrupt Enable (Bit 3)
The Timer 0 Interrupt Enable bit enables or disables the TImer0 Interrupt Enable. When this bit is reset, all pending Timer 0 interrupts are cleared.
1: Enable TM0 interrupt 0: Disable TM0 interrupt Reserved
The UART Interrupt Enable bit enables or disables the following UART hardware interrupts: UART TX, and UART RX.
1: Enable UART interrupt 0: Disable UART interrupt
Write all reserved bits with '0'.
Breakpoint Register [0xC014] [R/W] Figure 17. Breakpoint Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8
Register Description
Address (Bits [15:0])
The Breakpoint register holds the breakpoint address. When the program counter matches this address, the INT127 interrupt occurs. To clear this interrupt, write a zero value to this register.
The Address field is a 16-bit field containing the breakpoint address.
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USB Diagnostic Register [0xC03C] [R/W] Figure 18. USB Diagnostic Register
Bit # 15 Port 2B Diagnostic Enable R/W 0 7 ...Reserved Field Read/Write Default 0 14 Port 2A Diagnostic Enable R/W 0 6 Pull-down Enable R/W 0 13 Port 1B Diagnostic Enable R/W 0 5 LS Pull-up Enable R/W 0 12 Port 1A Diagnostic Enable R/W 0 4 FS Pull-up Enable R/W 0 0 3 Reserved 0 R/W 0 0 2 11 10 Reserved... 9 8
Field Read/Write Default Bit #
0 1 Force Select R/W 0
0 0
R/W 0
Register Description
Pull-down Enable (Bit 6)
The USB Diagnostic register provides control of diagnostic modes. It is intended for use by device characterization tests, not for normal operations. This register is read/write by the on-chip CPU but is write-only via the HPI port.
Port 2B Diagnostic Enable (Bit 15)
The Pull-down Enable bit enables or disables full-speed pull down resistors (pull down on both D+ and D-) for testing.
1: Enable pull down resistors on both D+ and D- 0: Disable pull down resistors on both D+ and D- LS Pull-up Enable (Bit 5)
The Port 2B Diagnostic Enable bit enables or disables Port 2B for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD 0: Do not apply test conditions Port 2A Diagnostic Enable (Bit 14)
The LS Pull-up Enable bit enables or disables a low-speed pull up resistor (pull up on D-) for testing.
1: Enable low-speed pull up resistor on D- 0: Pull-up resistor is not connected on D- FS Pull-up Enable (Bit 4)
The Port 2A Diagnostic Enable bit enables or disables Port 2A for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD 0: Do not apply test conditions Port 1B Diagnostic Enable (Bit 13)
The FS Pull-up Enable bit enables or disables a full-speed pull up resistor (pull up on D+) for testing.
1: Enable full-speed pull up resistor on D+ 0: Pull up resistor is not connected on D+ Force Select (Bits [2:0])
The Port 1B Diagnostic Enable bit enables or disables Port 1B for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD 0: Do not apply test conditions Port 1A Diagnostic Enable (Bit 12)
The Force Select field bit selects several different test condition states on the data lines (D+/D-). Refer to Table 24 for details.
Table 24. Force Select Definition Force Select [2:0] Data Line State
1xx 01x 001 000
Reserved
Assert SE0 Toggle JK Assert J Assert K
The Port 1A Diagnostic Enable bit enables or disables Port 1A for the test conditions selected in this register.
1: Apply any of the following enabled test conditions: J/K, DCK, SE0, RSF, RSL, PRD 0: Do not apply test conditions
Write all reserved bits with '0'.
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Memory Diagnostic Register [0xC03E] [W] Figure 19. Memory Diagnostic Register
Bit # 15 14 13 Reserved Field Read/Write Default Bit # Field Read/Write Default 0 0 0 0 0 0 0 0 7 0 6 0 5 0 4 Reserved 0 3 W 0 2 12 11 10 9 Memory Arbitration Select W 0 1 W 0 0 Monitor Enable W 0 8
Register Description
Reserved
The Memory Diagnostic register provides control of diagnostic modes.
Memory Arbitration Select (Bits[10:8])
Write all reserved bits with '0'.
External Memory Registers
The Memory Arbitration Select field is defined in Table 25.
Table 25. Memory Arbitration Select Memory Arbitration Select [3:0] Memory Arbitration Timing
There are four registers dedicated to controlling the external memory interface. Each of these registers are covered in this section and are summarized in Table 26.
Table 26. External Memory Control Registers Register Name Address R/W
111 110 101 100 011 010 001 000
Monitor Enable (Bit 0)
1/8, 7 of every 8 cycles dead 2/8, 6 of every 8 cycles dead 3/8, 5 of every 8 cycles dead 4/8, 4 of every 8 cycles dead 5/8, 3 of every 8 cycles dead 6/8, 2 of every 8 cycles dead 7/8, 1 of every 8 cycles dead 8/8, all cycles available
Extended Page 1 Map Register Extended Page 2 Map Register Upper Address Enable Register External Memory Control Register
0xC018 0xC01A 0xC038 0xC03A
R/W R/W R/W R/W
The Monitor Enable bit enables or disables monitor mode. In monitor mode the internal address bus is echoed to the external address pins.
1: Enable monitor mode 0: Disable monitor mode
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Extended Page n Map Register [R/W] * Extended Page 1 Map Register 0xC018 * Extended Page 2 Map Register 0xC01A Figure 20. Extended Page n Map Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8
Register Description
The Extended Page n Map register contains the Page n high-order address bits. These bits are always appended to accesses to the Page n Memory mapped space.
Address (Bits [15:0])
[21:13]) reflect the content of this register when the CPU accesses the address 0x8000-0x9FFF. For the SRAM mode, the address pin on [4:0] (Page n address [17:13]) is used. Set bit [8] (Page n address [21]) to `0', so that Page n reads/writes access external areas (SRAM, ROM or peripherals). nXMEMSEL is the external chip select for this space.
The Address field contains the high-order bits 28 to 13 of the Page n address. The address pins [8:0] (Page n address
Upper Address Enable Register [0xC038] [R/W] Figure 21. External Memory Control Register
Bit # Field Read/Write Default Bit # X 7 X 6 Reserved Field Read/Write Default X X X X X 5 X 4 15 14 13 12 Reserved X 3 Upper Address Enable R/W 0 X X X X 2 X 1 Reserved X 0 11 10 9 8
Register Description
The Upper Address Enable register enables/disables the four most significant bits of the external address A[18:15]. This register defaults to having the Upper Address disabled. Note that on power up, pins A[18:15] are driven high.
Upper Address Enable (Bit 3)
1: Enable A[18:15] of the external memory interface for general addressing. 0: Disable A[18:15], not available. Reserved
Write all reserved bits with '0'.
The Upper Address Enable bit enables/disables the four most significant bits of the external address A[18:15].
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External Memory Control Register [0xC03A] [R/W] Figure 22. External Memory Control Register
Bit # Field Read/Write Default Bit # Field Read/Write Default X 7 XROM Width Select R/W X R/W X X 6 15 Reserved 14 13 12 11 XMEM Width Select R/W X 3 XRAM Width Select R/W X R/W X R/W X R/W X 2 10 9 XMEM Wait Select R/W X 1 XRAM Wait Select R/W X R/W X R/W X 0 8 XRAM Merge XROM Merge Enable Enable R/W X 5 XROM Wait Select R/W X R/W X 4
Register Description
XROM Wait Select (Bits[6:4])
The External Memory Control register provides control of Wait States for the external SRAM or ROM. All wait states are based off of 48 MHz.
XRAM Merge Enable (Bit 13)
The XROM Wait Select field selects the external ROM wait state from 0 to 7.
XRAM Width Select (Bit 3)
The XRAM Width Select bit selects the external RAM width.
1: External memory = 8 0: External memory = 16 XRAM Wait Select (Bits[2:0])
The XRAM Merge Enable bit enables or disables the RAM merge feature. When the RAM merge feature is enabled, the nXRAMSEL is active whenever the nXMEMSEL is active.
1: Enable RAM merge 0: Disable RAM merge XROM Merge Enable (Bit 12)
The XRAM Wait Select field selects the external RAM wait state from 0 to 7.
Reserved
The XROM Merge Enable bit enables or disables the ROM merge feature. When the ROM merge feature is enabled, the nXROMSEL is active whenever the nXMEMSEL is active.
1: Enable ROM merge 0: Disable ROM merge XMEM Width Select (Bit 11)
Write all reserved bits with '0'.
Timer Registers
There are three registers dedicated to timer operations. Each of these registers are discussed in this section and are summarized in Table 27.
Table 27. Timer Registers Register Name Address R/W
The XMEM Width Select bit selects the extended memory width.
1: Extended memory = 8 0: Extended memory = 16 XMEM Wait Select (Bits [10:8])
Watchdog Timer Register Timer 0 Register Timer 1 Register
0xC00C 0xC010 0xC012
R/W R/W R/W
The XMEM Wait Select field selects the extended memory wait state from 0 to 7.
XROM Width Select (Bit 7)
The XROM Width Select bit selects the external ROM width.
1: External memory = 8 0: External memory = 16
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Watchdog Timer Register [0xC00C] [R/W] Figure 23. Watchdog Timer Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 7 ...Reserved R/W 0 6 R/W 0 5 Timeout Flag R/W 0 R/W 0 0 4 Period Select R/W 0 15 14 13 12 Reserved... R/W R/W 0 3 R/W 0 2 Lock Enable R/W 0 R/W 0 1 WDT Enable R/W 0 R/W 0 0 Reset Strobe W 0 11 10 9 8
Register Description
Lock Enable (Bit 2)
The Watchdog Timer register provides status and control over the Watchdog timer. The Watchdog timer can also interrupt the processor.
Timeout Flag (Bit 5)
The Lock Enable bit does not allow any writes to this register until a reset. In doing so the Watchdog timer can be set up and enabled permanently so that it can only be cleared on reset (the WDT Enable bit is ignored).
1: Watchdog timer permanently set 0: Watchdog timer not permanently set WDT Enable (Bit 1)
The Timeout Flag bit indicates if the Watchdog timer expired. The processor can read this bit after exiting a reset to determine if a Watchdog timeout occurred. This bit is cleared on the next external hardware reset.
1: Watchdog timer expired. 0: Watchdog timer did not expire. Period Select (Bits [4:3])
The WDT Enable bit enables or disables the Watchdog timer.
1: Enable Watchdog timer operation 0: Disable Watchdog timer operation Reset Strobe (Bit 0)
The Period Select field is defined in Table 28. If this time expires before the Reset Strobe bit is set, the internal processor is reset.
Table 28. Period Select Definition Period Select[4:3] 00 WDT Period Value 1.4 ms
The Reset Strobe is a write-only bit that resets the Watchdog timer count. Set this bit to `1' before the count expires to avoid a Watchdog trigger
1: Reset Count Reserved
01 10 11
5.5 ms 22.0 ms 66.0 ms
Write all reserved bits with '0'.
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Timer n Register [R/W] * Timer 0 Register 0xC010 * Timer 1 Register 0xC012 Figure 24. Timer n Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 ...Count R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 Count... R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 11 10 9 8
Register Description
The Timer n Register sets the Timer n count. Both Timer 0 and Timer 1 decrement by one every 1 s clock tick. Each can provide an interrupt to the CPU when the timer reaches zero.
Count (Bits [15:0])
functions for both USB host and USB peripheral options and is covered in this section and summarized in Table 29. USB Host only registers are covered in UART Interface on page 7, and USB device only registers are covered in External Memory Registers on page 23.
Table 29. General USB Registers Register Name Address (SIE1/SIE2) R/W
The Count field sets the Timer count.
General USB Registers
USB n Control Register
0xC08A/0xC0AA
R/W
There is one set of registers dedicated to general USB control. This set consists of two identical registers: one for Host/Device Port 1 and one for Host/Device Port 2. This register set has
USB n Control Register [R/W] * USB 1 Control Register 0xC08A * USB 2 Control Register 0xC0AA Figure 25. USB n Control Register
Bit # 15 Port B D+ Status R X 7 Port A Resistors Enable R/W 0 R/W 0 14 Port B D- Status R X 6 Port B Force D State R/W 0 R/W 0 13 Port A D+ Status R X 5 12 Port A D- Status R X 4 Port A Force D State R/W 0 11 LOB 10 LOA 9 Mode Select R/W 0 1 Port B SOF/EOP Enable R/W 0 8 Port B Resistors Enable R/W 0 0 Port A SOF/EOP Enable R/W 0
Field Read/Write Default Bit #
R/W 0 3
R/W 0 2 Suspend Enable R/W 0
Field Read/Write Default
Register Description
Port B D+ Status (Bit 15)
The USB n Control register is used in both host and device mode. It monitors and controls the SIE and the data lines of the USB ports. This register can be accessed by the HPI interface.
The Port B D+ Status bit is a read only bit that indicates the value of DATA+ on Port B.
1: D+ is HIGH 0: D+ is LOW
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Port B D- Status (Bit 14)
The Port B D- Status bit is a read only bit that indicates the value of DATA- on Port B.
1: D- is HIGH 0: D- is LOW Port A D+ Status (Bit 13)
single pull up resistor on either D+ or D-, determined by the LOA bit, is enabled. See Table 30 for details.
1: Enable pull up/pull down resistors 0: Disable pull up/pull down resistors Table 30. USB Data Line Pull Up and Pull Down Resistors L0A/ L0B Mode Select Port n Resistors Enable Function
The Port A D+ Status bit is a read only bit that indicates the value of DATA+ on Port A.
1: D+ is HIGH 0: D+ is LOW Port A D- Status (Bit 12)
X X 1 0
X 1 0 0
0 1 1 1
Pull up/Pull down on D+ and D- Disabled Pull down on D+ and D- Enabled Pull up on USB D- Enabled Pull up on USB D+ Enabled
The Port A D- Status bit is a read only bit that indicates the value of DATA- on Port A.
1: D- is HIGH 0: D- is LOW LOB (Bit 11)
Port B Force D State (Bits [6:5])
The LOB bit selects the speed of Port B.
1: Port B is set to low-speed mode 0: Port B is set to full-speed mode LOA (Bit 10)
The Port B Force D State field controls the forcing state of the D+ D- data lines for Port B. This field forces the state of the Port B data lines independent of the Port Select bit setting. See Table 31 for details.
Port A Force D State (Bits [4:3])
The LOA bit selects the speed of Port A.
1: Port A is set to low-speed mode 0: Port A is set to full-speed mode Mode Select (Bit 9)
The Port A Force D State field controls the forcing state of the D+ D- data lines for Port A. This field forces the state of the Port A data lines independent of the Port Select bit setting. See Table 31 for details.
Table 31. Port A/B Force D State Port A/B Force D State Function
The Mode Select bit sets the SIE for host or device operation. When set for device operation only one USB port is supported. The active port is selected by the Port Select bit in the Host n Count register.
1: Host mode 0: Device mode Port B Resistors Enable (Bit 8)
MSb 0 1 0 1
LSb 0 0 1 1 Normal Operation Force USB Reset, SE0 State Force J-State Force K-State
Suspend Enable (Bit 2)
The Port B Resistors Enable bit enables or disables the pull up/pull down resistors on Port B. When enabled, the Mode Select bit and LOB bit of this register set the pull up/pull down resistors appropriately. When the Mode Select is set for Host mode, the pull down resistors on the data lines (D+ and D-) are enabled. When the Mode Select is set for Device mode, a single pull up resistor on either D+ or D-, determined by the LOB bit, is enabled. See Table 30 for details.
1: Enable pull up/pull down resistors 0: Disable pull up/pull down resistors Port A Resistors Enable (Bit 7)
The Suspend Enable bit enables or disables the suspend feature on both ports. When suspend is enabled the USB transceivers are powered down and cannot transmit or received USB packets but can still monitor for a wakeup condition.
1: Enable suspend 0: Disable suspend Port B SOF/EOP Enable (Bit 1)
The Port A Resistors Enable bit enables or disables the pull up/pull down resistors on Port A. When enabled, the Mode Select bit and LOA bit of this register set the pull up/pull down resistors appropriately. When the Mode Select is set for Host mode, the pull down resistors on the data lines (D+ and D-) are enabled. When the Mode Select is set for Device mode, a
The Port B SOF/EOP Enable bit is only applicable in host mode. In device mode, this bit must be written as `0'. In host mode this bit enables or disables SOFs or EOPs for Port B. Either SOFs or EOPs are generated depending on the LOB bit in the USB n Control register when Port B is active.
1: Enable SOFs or EOPs 0: Disable SOFs or EOPs
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Port A SOF/EOP Enable (Bit 0)
Reserved
The Port A SOF/EOP Enable bit is only applicable in host mode. In device mode this bit must be written as `0'. In host mode this bit enables or disables SOFs or EOPs for Port A. Either SOFs or EOPs are generated depending on the LOA bit in the USB n Control register when Port A is active.
1: Enable SOFs or EOPs 0: Disable SOFs or EOPs USB Host Only Registers
Write all reserved bits with '0'.
There are twelve sets of dedicated registers for USB host only operation. Each set consists of two identical registers (unless otherwise noted), one for Host Port 1 and one for Host Port 2.
Table 32. USB Host Only Register Register Name
These register sets are covered in this section and summarized in Table 32.
Address (Host 1/Host 2)
R/W
Host n Control Register Host n Address Register Host n Count Register Host n Endpoint Status Register Host n PID Register Host n Count Result Register Host n Device Address Register Host n Interrupt Enable Register Host n Status Register Host n SOF/EOP Count Register Host n SOF/EOP Counter Register Host n Frame Register
Host n Control Register [R/W] * Host 1 Control Register 0xC080 * Host 2 Control Register 0xC0A0
0xC080/0xC0A0 0xC082/0xC0A2 0xC084/0xC0A4 0xC086/0xC0A6 0xC086/0xC0A6 0xC088/0xC0A8 0xC088/0xC0A8 0xC08C/0xC0AC 0xC090/0xC0B0 0xC092/0xC0B2 0xC094/0xC0B4 0xC096/0xC0B6
R/W R/W R/W R W R W R/W R/W R/W R R
Figure 26. Host n Control Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 0 7 Preamble Enable R/W 0 0 6 Sequence Select R/W 0 0 5 Sync Enable R/W 0 0 4 ISO Enable R/W 0 0 15 14 13 12 Reserved 0 3 0 2 Reserved 0 0 0 1 0 0 Arm Enable R/W 0 11 10 9 8
Register Description
Preamble Enable (Bit 7)
The Host n Control register allows high level USB transaction control.
The Preamble Enable bit enables or disables the transmission of a preamble packet before all low-speed packets. Set this bit only when communicating with a low-speed device.
1: Enable Preamble packet 0: Disable Preamble packet
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Sequence Select (Bit 6)
ISO Enable (Bit 4)
The Sequence Select bit sets the data toggle for the next packet. This bit has no effect on receiving data packets; sequence checking must be handled in firmware.
1: Send DATA1 0: Send DATA0 Sync Enable (Bit 5)
The ISO Enable bit enables or disables an isochronous transaction.
1: Enable isochronous transaction 0: Disable isochronous transaction Arm Enable (Bit 0)
The Sync Enable bit synchronizes the transfer with the SOF packet in full-speed mode and the EOP packet in low-speed mode.
1: The next enabled packet is transferred after the SOF or EOP packet is transmitted 0: The next enabled packet is transferred as soon as the SIE is free
The Arm Enable bit arms an endpoint and starts a transaction. This bit is automatically cleared to `0' when a transaction is complete.
1: Arm endpoint and begin transaction 0: Endpoint disarmed
Reserved Write all reserved bits with '0'.
Host n Address Register [R/W] * Host 1 Address Register 0xC082 * Host 2 Address Register 0xC0A2 Figure 27. Host n Address Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8
Register Description
Address (Bits [15:0])
The Host n Address register is used as the base pointer into memory space for the current host transactions.
The Address field sets the address pointer into internal RAM or ROM.
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Host n Count Register [R/W] * Host 1 Count Register 0xC084. * Host 2 Count Register 0xC0A4. Figure 28. Host n Count Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 15 Reserved 14 Port Select R/W 0 6 0 5 0 4 ...Count R/W 0 R/W 0 R/W 0 R/W 0 13 12 Reserved 0 3 0 2 R/W 0 1 11 10 9 Count... R/W 0 0 8
Register Description
Table 33. Port Select Definition Port Select Host/Device 1 Active Port Host/Device 2 Active Port
The Host n Count register is used to hold the number of bytes (packet length) for the current transaction. The maximum packet length is 1023 bytes in ISO mode. The Host Count value is used to determine how many bytes to transmit, or the maximum number of bytes to receive. If the number of received bytes is greater then the Host Count value then an overflow condition is flagged by the Overflow bit in the Host n Endpoint Status register.
Port Select (Bit 14)
0 1
Count (Bits [9:0])
A B
A B
The Port Select bit selects which of the two active ports is selected and is summarized in Table 33.
1: Port 1B or Port 2B is enabled 0: Port 1A or Port 2A is enabled Host n Endpoint Status Register [R] * Host 1 Endpoint Status Register 0xC086 * Host 2 Endpoint Status Register 0xC0A6
The Count field sets the value for the current transaction data packet length. This value is retained when switching between host and device mode, and back again.
Reserved
Write all reserved bits with '0'.
Figure 29. Host n Endpoint Status Register
Bit # Field Read/Write Default Bit # 0 7 Stall Flag Field Read/Write Default R 0 R 0 0 6 NAK Flag 0 5 Length Exception Flag R 0 0 4 Reserved 15 14 Reserved 13 12 11 Overflow Flag R 0 3 Sequence Status R 0 10 Underflow Flag R 0 2 Timeout Flag R 0 0 1 Error Flag R 0 9 Reserved 0 0 ACK Flag R 0 8
0
Register Description
The Host n Endpoint Status register is a read only register that provides status for the last USB transaction.
Overflow Flag (Bit 11)
in the Host n Count register. The Overflow Flag must be checked in response to a Length Exception signified by the Length Exception Flag set to `1'.
1: Overflow condition occurred 0: Overflow condition did not occur
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Underflow Flag (Bit 10)
The Underflow Flag bit indicates that the received data in the last data transaction was less than the maximum length specified in the Host n Count register. The Underflow Flag must be checked in response to a Length Exception signified by the Length Exception Flag set to `1'.
1: Underflow condition occurred 0: Underflow condition did not occur Stall Flag (Bit 7)
set to `0' when an error is detected in the transaction and the Error bit is set. 1: DATA1 0: DATA0
Timeout Flag (Bit 2)
The Stall Flag bit indicates that the peripheral device replied with a Stall in the last transaction. 1: Device returned Stall 0: Device did not return Stall
NAK Flag (Bit 6)
The Timeout Flag bit indicates if a timeout condition occurred for the last transaction. A timeout condition can occur when a device either takes too long to respond to a USB host request or takes too long to respond with a handshake. 1: Timeout occurred 0: Timeout did not occur
Error Flag (Bit 1)
The NAK Flag bit indicates that the peripheral device replied with a NAK in the last transaction. 1: Device returned NAK 0: Device did not return NAK
Length Exception Flag (Bit 5)
The Error Flag bit indicates a transaction failed for any reason other than the following: timeout, receiving a NAK, or receiving a STALL. Overflow and Underflow are not considered errors and do not affect this bit. CRC5 and CRC16 errors result in an Error flag along with receiving incorrect packet types. 1: Error detected 0: No error detected
ACK Flag (Bit 0)
The Length Exception Flag bit indicates that the received data in the data stage of the last transaction does not equal the maximum Host Count specified in the Host n Count register. A Length Exception can either mean an overflow or underflow and the Overflow and Underflow flags (bits 11 and 10, respectively) must be checked to determine which event occurred. 1: An overflow or underflow condition occurred 0: An overflow or underflow condition did not occur
Sequence Status (Bit 3)
The ACK Flag bit indicates two different conditions depending on the transfer type. For non-isochronous transfers, this bit represents a transaction ending by receiving or sending an ACK packet. For isochronous transfers, this bit represents a successful transaction that is not represented by an ACK packet.
1: For non-isochronous transfers, the transaction was ACKed. For isochronous transfers, the transaction was completed successfully 0: For non-isochronous transfers, the transaction was not ACKed. For isochronous transfers, the transaction did not complete successfully
The Sequence Status bit indicates the state of the last received data toggle from the device. Firmware is responsible for monitoring and handling the sequence status. The Sequence bit is only valid if the ACK bit is set to `1'. The Sequence bit is
Host n PID Register [W] * Host 1 PID Register 0xC086 * Host 2 PID Register 0xC0A6 Figure 30. Host n PID Register
Bit # Field Read/Write Default Bit # Field Read/Write Default W 0 W 0 0 7 0 6 PID Select W 0 W 0 W 0 0 5 0 4 15 14 13 12 Reserved 0 3 0 2 W 0 0 1 W 0 0 0 W 0 11 10 9 8
Endpoint Select
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Register Description
Endpoint Select (Bits [3:0])
The Host n PID register is a write only register that provides the PID and Endpoint information to the USB SIE to be used in the next transaction.
PID Select (Bits [7:4])
The Endpoint field allows addressing of up to 16 different endpoints.
Reserved
Write all reserved bits with '0'.
The PID Select field is defined in Table 34. ACK and NAK tokens are automatically sent based on settings in the Host n Control register and do not need to be written in this register.
Table 34. PID Select Definition PID TYPE PID Select [7:4]
SETUP IN OUT SOF PREAMBLE NAK STALL DATA0 DATA1
1101 (D Hex) 1001 (9 Hex) 0001 (1 Hex) 0101 (5 Hex) 1100 (C Hex) 1010 (A Hex) 1110 (E Hex) 0011 (3 Hex) 1011 (B Hex)
Host n Count Result Register [R] * Host 1 Count Result Register 0xC088 * Host 2 Count Result Register 0xC0A8 Figure 31. Host n Count Result Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R 0 R 0 R 0 R 0 R 0 7 R 0 6 R 0 5 R 0 4 ...Result R 0 R 0 R 0 R 0 15 14 13 12 Result... R 0 3 R 0 2 R 0 1 R 0 0 11 10 9 8
Register Description
Result (Bits [15:0])
The Host n Count Result register is a read only register that contains the size difference in bytes between the Host Count Value specified in the Host n Count register and the last packet received. If an overflow or underflow condition occurs, that is the received packet length differs from the value specified in the Host n Count register, the Length Exception Flag bit in the Host n Endpoint Status register is set. The value in this register is only value when the Length Exception Flag bit is set and the Error Flag bit is not set, both bits are in the Host n Endpoint Status register.
The Result field contains the differences in bytes between the received packet and the value specified in the Host n Count register. If an overflow condition occurs, Result [15:10] is set to `111111', a 2's complement value indicating the additional byte count of the received packet. If an underflow condition occurs, Result [15:0] indicates the excess bytes count (number of bytes not used).
Reserved
Write all reserved bits with '0'.
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Host n Device Address Register [W] * Host 1 Device Address Register 0xC088 * Host 2 Device Address Register 0xC0A8 Figure 32. Host n Device Address Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 0 7 ...Reserved 0 W 0 W 0 W 0 0 6 0 5 0 4 15 14 13 12 Reserved... 0 3 Address W 0 W 0 W 0 W 0 0 2 0 1 0 0 11 10 9 8
Register Description
Address (Bits [6:0])
The Host n Device Address register is a write only register that contains the USB Device Address that the host wants to communicate with.
The Address field contains the value of the USB address for the next device that the host is going to communicate with. This value must be written by firmware.
Reserved
Write all reserved bits with '0'.
Host n Interrupt Enable Register [R/W] * Host 1 Interrupt Enable Register 0xC08C * Host 2 Interrupt Enable Register 0xC0AC Figure 33. Host n Interrupt Enable Register
Bit # 15 VBUS Interrupt Enable R/W 0 7 14 ID Interrupt Enable R/W 0 6 0 5 0 4 13 12 Reserved 11 10 9 SOF/EOP Interrupt Enable 0 3 0 2 Reserved R/W 0 1 8 Reserved
Field Read/Write Default Bit #
0 0 Done Interrupt Enable
Field Read/Write Default
Port B Port A Port B Connect Port A Connect Wake Interrupt Wake Interrupt Change Change Enable Enable Interrupt Interrupt Enable Enable R/W 0 R/W 0 R/W 0 R/W 0 0
0
0
R/W 0
Register Description
1: Enable VBUS interrupt 0: Disable VBUS interrupt ID Interrupt Enable (Bit 14)
The Host n Interrupt Enable register enables control over host related interrupts. In this register a bit set to `1' enables the corresponding interrupt while `0' disables the interrupt.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled this interrupt triggers on both the rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.
The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.
1: Enable ID interrupt 0: Disable ID interrupt
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SOF/EOP Interrupt Enable (Bit 9)
1: Enable Connect Change interrupt 0: Disable Connect Change interrupt Port A Connect Change Interrupt Enable (Bit 4)
The SOF/EOP Interrupt Enable bit enables or disables the SOF/EOP timer interrupt
1: Enable SOF/EOP timer interrupt 0: Disable SOF/EOP timer interrupt Port B Wake Interrupt Enable (Bit 7)
The Port B Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port B
1: Enable remote wakeup interrupt for Port B 0: Disable remote wakeup interrupt for Port B Port A Wake Interrupt Enable (Bit 6)
The Port A Connect Change Interrupt Enable bit enables or disables the Connect Change interrupt on Port A. This interrupt triggers when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state).
1: Enable Connect Change interrupt 0: Disable Connect Change interrupt Done Interrupt Enable (Bit 0)
The Port A Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port A
1: Enable remote wakeup interrupt for Port A 0: Disable remote wakeup interrupt for Port A Port B Connect Change Interrupt Enable (Bit 5)
The Done Interrupt Enable bit enables or disables the USB Transfer Done interrupt. The USB Transfer Done triggers when either the host responds with an ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout. This interrupt is used for both Port A and Port B.
1: Enable USB Transfer Done interrupt 0: Disable USB Transfer Done interrupt Reserved
The Port B Connect Change Interrupt Enable bit enables or disables the Port B Connect Change interrupt on Port B. This interrupt triggers when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state).
Host n Status Register [R/W] * Host 1 Status Register 0xC090 * Host 2 Status Register 0xC0B0
Write all reserved bits with '0'.
Figure 34. Host n Status Register
Bit # Field Read/Write Default Bit # 7 Port B Wake Interrupt Flag R/W X 15 VBUS Interrupt Flag R/W X 6 Port A Wake Interrupt Flag R/W X 14 ID Interrupt Flag R/W X 5 X X 4 13 12 Reserved X 3 Port B SE0 Status R/W X X 2 Port A SE0 Status R/W X 11 10 9 SOF/EOP Interrupt Flag R/W X 1 Reserved 8 Reserved X 0 Done Interrupt Flag R/W X
Field Read/Write Default
Port B Connect Port A Connect Change Change Interrupt Interrupt Flag Flag R/W X R/W X
X
Register Description
1: Interrupt triggered 0: Interrupt did not trigger ID Interrupt Flag (Bit 14)
The Host n Status register provides status information for host operation. Pending interrupts can be cleared by writing a `1' to the corresponding bit. This register can be accessed by the HPI interface.
VBUS Interrupt Flag (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Host 1 and is a reserved bit in Host 2.
The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin. This bit is only available for Host 1 and is a reserved bit in Host 2.
1: Interrupt triggered 0: Interrupt did not trigger
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SOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates the status of the SOF/EOP Timer interrupt. This bit triggers `1' when the SOF/EOP timer expires.
1: Interrupt triggered 0: Interrupt did not trigger Port B Wake Interrupt Flag (Bit 7)
triggers `1' on either a rising edge or falling edge of a USB Reset condition (device inserted or removed). Together with the Port A SE0 Status bit, it can be determined whether a device was inserted or removed.
1: Interrupt triggered 0: Interrupt did not trigger Port B SE0 Status (Bit 3)
The Port B Wake Interrupt Flag bit indicates remote wakeup on PortB.
1: Interrupt triggered 0: Interrupt did not trigger Port A Wake Interrupt Flag (Bit 6)
The Port B SE0 Status bit indicates if Port B is in a SE0 state or not. Together with the Port B Connect Change Interrupt Flag bit, it can be determined whether a device was inserted (non-SE0 condition) or removed (SE0 condition).
1: SE0 condition 0: Non-SE0 condition Port A SE0 Status (Bit 2)
The Port A Wake Interrupt Flag bit indicates remote wakeup on PortA.
1: Interrupt triggered 0: Interrupt did not trigger Port B Connect Change Interrupt Flag (Bit 5)
The Port A SE0 Status bit indicates if Port A is in a SE0 state or not. Together with the Port A Connect change Interrupt Flag bit, it can be determined whether a device was inserted (non-SE0 condition) or removed (SE0 condition).
1: SE0 condition 0: Non-SE0 condition Done Interrupt Flag (Bit 0)
The Port B Connect Change Interrupt Flag bit indicates the status of the Connect Change interrupt on Port B. This bit triggers `1' on either a rising edge or falling edge of a USB Reset condition (device inserted or removed). Together with the Port B SE0 Status bit, it can be determined whether a device was inserted or removed.
1: Interrupt triggered 0: Interrupt did not trigger Port A Connect Change Interrupt Flag (Bit 4)
The Done Interrupt Flag bit indicates the status of the USB Transfer Done interrupt. The USB Transfer Done triggers when either the host responds with an ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout. This interrupt is used for both Port A and Port B.
1: Interrupt triggered 0: Interrupt did not trigger
The Port A Connect Change Interrupt Flag bit indicates the status of the Connect Change interrupt on Port A. This bit
Host n SOF/EOP Count Register [R/W] * Host 1 SOF/EOP Count Register 0xC092 * Host 2 SOF/EOP Count Register 0xC0B2
Figure 35. Host n SOF/EOP Count Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 1 R/W 1 R/W 1 R/W 0 0 7 15 Reserved 0 6 R/W 1 5 R/W 0 4 ...Count R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 3 14 13 12 11 Count... R/W 1 2 R/W 1 1 R/W 0 0 10 9 8
Register Description
The Host n SOF/EOP Count register contains the SOF/EOP Count Value that is loaded into the SOF/EOP counter. This value is loaded each time the SOF/EOP counter counts down to zero. The default value set in this register at power up is 0x2EE0 which generates a 1 ms time frame. The SOF/EOP counter is a down counter decremented at a 12 MHz rate.
When this register is read, the value returned is the programmed SOF/EOP count value.
Count (Bits [13:0])
The Count field sets the SOF/EOP counter duration.
Reserved
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Host n SOF/EOP Counter Register [R] * Host 1 SOF/EOP Counter Register 0xC094 * Host 2 SOF/EOP Counter Register 0xC0B4 Figure 36. Host n SOF/EOP Counter Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R X R X R X R X X 7 15 Reserved X 6 R X 5 R X 4 ...Counter R X R X R X R X R X 3 14 13 12 11 Counter... R X 2 R X 1 R X 0 10 9 8
Register Description
Counter (Bits [13:0])
The Host n SOF/EOP Counter register contains the current value of the SOF/EOP down counter. This value can be used to determine the time remaining in the current frame.
Host n Frame Register [R] * Host 1 Frame Register 0xC096 * Host 2 Frame Register 0xC0B6
The Counter field contains the current value of the SOF/EOP down counter.
Figure 37. Host n Frame Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R 0 R 0 R 0 R 0 0 7 0 6 15 14 13 Reserved 0 5 0 4 ...Frame R 0 R 0 R 0 R 0 0 3 R 0 2 12 11 10 9 Frame... R 0 1 R 0 0 8
Register Description
Frame (Bits [10:0])
The Host n Frame register maintains the next frame number to be transmitted (current frame number + 1). This value is updated after each SOF transmission. This register resets to 0x0000 after each CPU write to the Host n SOF/EOP Count register (Host 1: 0xC092 Host 2: 0xC0B2).
The Frame field contains the next frame number to be transmitted.
Reserved
Write all reserved bits with '0'.
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USB Device Only Registers
There are eleven sets of USB Device Only registers. All sets consist of at least two registers, one for Device Port 1 and one for Device Port 2. In addition, each Device port has eight
Table 35. USB Device Only Registers Register Name
possible endpoints. This gives each endpoint register set eight registers for each Device Port for a total of sixteen registers per set. The USB Device Only registers are covered in this section and summarized in Table 35.
Address (Device 1/Device 2)
R/W
Device n Endpoint n Control Register Device n Endpoint n Address Register Device n Endpoint n Count Register Device n Endpoint n Status Register Device n Endpoint n Count Result Register Device n Port Select Register Device n Interrupt Enable Register Device n Address Register Device n Status Register Device n Frame Number Register Device n SOF/EOP Count Register
0x02n0 0x02n2 0x02n4 0x02n6 0x02n8 0xC084/0xC0A4 0xC08C/0xC0AC 0xC08E/0xC0AE 0xC090/0xCB0 0xC092/0xC0B2 0xC094/0xC0B4
R/W R/W R/W R/W R/W R/W R/W R/W R/W R W
Device n Endpoint n Control Register [R/W] * Device n Endpoint 0 Control Register [Device 1: 0x0200 Device 2: 0x0280] * Device n Endpoint 1 Control Register [Device 1: 0x0210 Device 2: 0x0290] * Device n Endpoint 2 Control Register [Device 1: 0x0220 Device 2: 0x02A0] * Device n Endpoint 3 Control Register [Device 1: 0x0230 Device 2: 0x02B0] * Device n Endpoint 4 Control Register [Device 1: 0x0240 Device 2: 0x02C0] * Device n Endpoint 5 Control Register [Device 1: 0x0250 Device 2: 0x02D0] * Device n Endpoint 6 Control Register [Device 1: 0x0260 Device 2: 0x02E0] * Device n Endpoint 7 Control Register [Device 1: 0x0270 Device 2: 0x02F0] Figure 38. Device n Endpoint n Control Register
Bit # Field Read/Write Default Bit # X 7 IN/OUT Ignore Enable R/W X X 6 Sequence Select R/W X X 5 Stall Enable R/W X X 4 ISO Enable R/W X 15 14 13 12 Reserved X 3 NAK Interrupt Enable R/W X X 2 Direction Select R/W X X 1 Enable X 0 Arm Enable R/W X 11 10 9 8
Field Read/Write Default
R/W X
Register Description
IN/OUT Ignore Enable (Bit 7)
The Device n Endpoint n Control register provides control over a single EP in device mode. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Control register.
The IN/OUT Ignore Enable bit forces endpoint 0 (EP0) to ignore all IN and OUT requests. Set this bit so that EP0 only accepts Setup packets at the start of each transfer. Clear this bit to accept IN/OUT transactions. This bit only applies to EP0.
1: Ignore IN/OUT requests 0: Do not ignore IN/OUT requests
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Sequence Select (Bit 6)
Direction Select (Bit 2)
The Sequence Select bit determines whether a DATA0 or a DATA1 is sent for the next data toggle. This bit has no effect on receiving data packets; sequence checking must be handled in firmware. 1: Send a DATA1 0: Send a DATA0
Stall Enable (Bit 5)
The Stall Enable bit sends a Stall in response to the next request (unless it is a setup request, which are always ACKed). This is a sticky bit and continues to respond with Stalls until cleared by firmware. 1: Send Stall 0: Do not send Stall
ISO Enable (Bit 4)
The Direction Select bit needs to be set according to the expected direction of the next data stage in the next transaction. If the data stage direction is different from what is set in this bit, it gets NAKed and either the IN Exception Flag or the OUT Exception Flag is set in the Device n Endpoint n Status register. If a setup packet is received and the Direction Select bit is set incorrectly, the setup is ACKed and the Setup Status Flag is set (refer to the setup bit of the Device n Endpoint n Status Register [R/W] on page 41 for details).
1: OUT transfer (host to device) 0: IN transfer (device to host) Enable (Bit 1)
The ISO Enable bit enables and disables an isochronous transaction. This bit is only valid for EPs 1-7 and has no function for EP0. 1: Enable isochronous transaction 0: Disable isochronous transaction
NAK Interrupt Enable (Bit 3)
Set the Enable bit to allow transfers to the endpoint. If Enable is set to `0' then all USB traffic to this endpoint is ignored. If Enable is set `1' and Arm Enable (bit 0) is set `0' then NAKs are automatically returned from this endpoint (except setup packets which are always ACKed as long as the Enable bit is set).
1: Enable transfers to an endpoint 0: Do not allow transfers to an endpoint Arm Enable (Bit 0)
The NAK Interrupt Enable bit enables and disables the generation of an Endpoint n interrupt when the device responds to the host with a NAK. The Endpoint n Interrupt Enable bit in the Device n Interrupt Enable register must also be set. When a NAK is sent to the host, the corresponding EP Interrupt Flag in the Device n Status register is set. In addition, the NAK Flag in the Device n Endpoint n Status register is set. 1: Enable NAK interrupt 0: Disable NAK interrupt
The Arm Enable bit arms the endpoint to transfer or receive a packet. This bit is cleared to `0' when a transaction is complete.
1: Arm endpoint 0: Endpoint disarmed Reserved
Write all reserved bits with '0'.
Device n Endpoint n Address Register [R/W] * Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282] * Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292] * Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2] * Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2] * Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2] * Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2] * Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2] * Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2] Figure 39. Device n Endpoint n Address Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W X R/W X R/W X R/W X R/W X 7 R/W X 6 R/W X 5 R/W X 4 ...Address R/W X R/W X R/W X R/W X 15 14 13 12 Address... R/W X 3 R/W X 2 R/W X 1 R/W X 0 11 10 9 8
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Register Description
Address (Bits [15:0])
The Device n Endpoint n Address register is used as the base pointer into memory space for the current Endpoint transaction. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Address register.
The Address field sets the base address for the current transaction on a signal endpoint.
Device n Endpoint n Count Register [R/W] * Device n Endpoint 0 Count Register [Device 1: 0x0204 Device 2: 0x0284] * Device n Endpoint 1 Count Register [Device 1: 0x0214 Device 2: 0x0294] * Device n Endpoint 2 Count Register [Device 1: 0x0224 Device 2: 0x02A4] * Device n Endpoint 3 Count Register [Device 1: 0x0234 Device 2: 0x02B4] * Device n Endpoint 4 Count Register [Device 1: 0x0244 Device 2: 0x02C4] * Device n Endpoint 5 Count Register [Device 1: 0x0254 Device 2: 0x02D4] * Device n Endpoint 6 Count Register [Device 1: 0x0264 Device 2: 0x02E4] * Device n Endpoint 7 Count Register [Device 1: 0x0274 Device 2: 0x02F4] Figure 40. Device n Endpoint n Count Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W X R/W X R/W X R/W X X 7 X 6 X 5 15 14 13 Reserved X 4 ...Count R/W X R/W X R/W X R/W X X 3 X 2 R/W X 1 12 11 10 9 Count... R/W X 0 8
Register Description
Count (Bits [9:0])
The Device n Endpoint n Count register designates the maximum packet size that can be received from the host for OUT transfers for a single endpoint. This register also designates the packet size to be sent to the host in response to the next IN token for a single endpoint. The maximum packet length is 1023 bytes in ISO mode. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Count register.
The Count field sets the current transaction packet length for a single endpoint.
Reserved
Write all reserved bits with '0'.
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Device n Endpoint n Status Register [R/W] * Device n Endpoint 0 Status Register [Device 1: 0x0206 Device 2: 0x0286] * Device n Endpoint 1 Status Register [Device 1: 0x0216 Device 2: 0x0296] * Device n Endpoint 2 Status Register [Device 1: 0x0226 Device 2: 0x02A6] * Device n Endpoint 3 Status Register [Device 1: 0x0236 Device 2: 0x02B6] * Device n Endpoint 4 Status Register [Device 1: 0x0246 Device 2: 0x02C6] * Device n Endpoint 5 Status Register [Device 1: 0x0256 Device 2: 0x02D6] * Device n Endpoint 6 Status Register [Device 1: 0x0266 Device 2: 0x02E6] * Device n Endpoint 7 Status Register [Device 1: 0x0276 Device 2: 0x02F6] Figure 41. Device n Endpoint n Status Register
Bit # Field Read/Write Default Bit # Field Read/Write Default X 7 Stall Flag R/W X X 6 NAK Flag R/W X X 5 Length Exception Flag R/W X X 4 Setup Flag R/W X 15 14 Reserved 13 12 11 Overflow Flag R/W X 3 Sequence Flag R/W X 10 Underflow Flag R/W X 2 Timeout Flag R/W X 9 8 OUT IN Exception Flag Exception Flag R/W X 1 Error Flag R/W X R/W X 0 ACK Flag R/W X
Register Description
1: Received OUT when armed for IN 0: Received IN when armed for IN IN Exception Flag (Bit 8)
The Device n Endpoint n Status register provides packet status information for the last transaction received or transmitted. This register is updated in hardware and does not need to be cleared by firmware. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Status register. The Device n Endpoint n Status register is a memory based register that must be initialized to 0x0000 before USB Device operations are initiated. After initialization, do not write to this register again.
Overflow Flag (Bit 11)
The IN Exception Flag bit indicates when the device received an IN packet when armed for an OUT.
1: Received IN when armed for OUT 0: Received OUT when armed for OUT Stall Flag (Bit 7)
The Stall Flag bit indicates that a Stall packet was sent to the host.
1: Stall packet was sent to the host 0: Stall packet was not sent NAK Flag (Bit 6)
The Overflow Flag bit indicates that the received data in the last data transaction exceeded the maximum length specified in the Device n Endpoint n Count register. The Overflow Flag must be checked in response to a Length Exception signified by the Length Exception Flag set to `1'.
1: Overflow condition occurred 0: Overflow condition did not occur Underflow Flag (Bit 10)
The NAK Flag bit indicates that a NAK packet was sent to the host.
1: NAK packet was sent to the host 0: NAK packet was not sent Length Exception Flag (Bit 5)
The Underflow Flag bit indicates that the received data in the last data transaction was less then the maximum length specified in the Device n Endpoint n Count register. The Underflow Flag must be checked in response to a Length Exception signified by the Length Exception Flag set to `1'.
1: Underflow condition occurred 0: Underflow condition did not occur OUT Exception Flag (Bit 9)
The Length Exception Flag bit indicates the received data in the data stage of the last transaction does not equal the maximum Endpoint Count specified in the Device n Endpoint n Count register. A Length Exception can either mean an overflow or underflow and the Overflow and Underflow flags (bits 11 and 10 respectively) must be checked to determine which event occurred.
1: An overflow or underflow condition occurred 0: An overflow or underflow condition did not occur
The OUT Exception Flag bit indicates when the device received an OUT packet when armed for an IN. Document #: 38-08015 Rev. *H
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Setup Flag (Bit 4)
The Setup Flag bit indicates that a setup packet was received. In device mode setup packets are stored at memory location 0x0300 for Device 1 and 0x0308 for Device 2. Setup packets are always accepted regardless of the Direction Select and Arm Enable bit settings as long as the Device n EP n Control register Enable bit is set.
1: Setup packet was received 0: Setup packet was not received Sequence Flag (Bit 3)
can occur if the device sends a data packet in response to an IN request but then does not receive a handshake packet in a predetermined time. It can also occur if the device does not receive the data stage of an OUT transfer in time.
1: Timeout occurred 0: Timeout condition did not occur Error Flag (Bit 2)
The Error Flag bit is set if a CRC5 and CRC16 error occurs, or if an incorrect packet type is received. Overflow and underflow are not considered errors and do not affect this bit.
1: Error occurred 0: Error did not occur ACK Flag (Bit 0)
The Sequence Flag bit indicates whether the last data toggle received was a DATA1 or a DATA0. This bit has no effect on receiving data packets; sequence checking must be handled in firmware.
1: DATA1 was received 0: DATA0 was received Timeout Flag (Bit 2)
The ACK Flag bit indicates whether the last transaction was ACKed.
1: ACK occurred 0: ACK did not occur
The Timeout Flag bit indicates whether a timeout condition occurred on the last transaction. On the device side, a timeout
Device n Endpoint n Count Result Register [R/W] * Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288] * Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298] * Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8] * Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8] * Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8] * Device n Endpoint 5 Count Result Register [Device 1: 0x0258 Device 2: 0x02D8] * Device n Endpoint 6 Count Result Register [Device 1: 0x0268 Device 2: 0x02E8] * Device n Endpoint 7 Count Result Register [Device 1: 0x0278 Device 2: 0x02F8] Figure 42. Device n Endpoint n Count Result Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W X R/W X R/W X R/W X R/W X 7 R/W X 6 R/W X 5 R/W X 4 ...Result R/W X R/W X R/W X R/W X 15 14 13 12 Result... R/W X 3 R/W X 2 R/W X 1 R/W X 0 11 10 9 8
Register Description
The Device n Endpoint n Count Result register contains the size difference in bytes between the Endpoint Count specified in the Device n Endpoint n Count register and the last packet received. If an overflow or underflow condition occurs, that is, the received packet length differs from the value specified in the Device n Endpoint n Count register, the Length Exception Flag bit in the Device n Endpoint n Status register is set. The value in this register is only valued when the Length Exception Flag bit is set and the Error Flag bit is not set; both bits are in the Device n Endpoint n Status register.
The Device n Endpoint n Count Result register is a memory-based register that must be initialized to 0x0000 before USB Device operations are initiated. After initialization, do not write to this register again.
Result (Bits [15:0])
The Result field contains the differences in bytes between the received packet and the value specified in the Device n Endpoint n Count register. If an overflow condition occurs, Result [15:10] is set to `111111', a 2's complement value indicating the additional byte count of the received packet. If
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an underflow condition occurs, Result [15:0] indicates the excess bytes count (number of bytes not used).
Reserved
Write all reserved bits with `0'.
Device n Port Select Register [R/W] * Device n Port Select Register 0xC084 * Device n Port Select Register 0xC0A4 Figure 43. Device n Port Select Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 0 0 0 7 15 Reserved 14 Port Select R/W 0 6 0 5 0 4 ...Reserved 0 0 0 0 0 3 13 12 11 Reserved... 0 2 0 1 0 0 10 9 8
Register Description
Port Select (Bit 14)
The Device n Port Select register selects either port A or port B for the static device port.
The Port Select bit selects which of the two ports is enabled.
1: Port 1B or Port 2B is enabled 0: Port 1A or Port 2A is enabled
Device n Interrupt Enable Register [R/W] * Device 1 Interrupt Enable Register 0xC08C * Device 2 Interrupt Enable Register 0xC0AC Figure 44. Device n Interrupt Enable Register
Bit # 15 VBUS Interrupt Enable Field Read/Write Default Bit # Field Read/Write Default R/W 0 7 EP7 Interrupt Enable R/W 0 R/W 0 6 EP6 Interrupt Enable R/W 0 0 5 EP5 Interrupt Enable R/W 0 0 4 EP4 Interrupt Enable R/W 0 14 ID Interrupt Enable 13 Reserved 12 11 SOF/EOP Timeout Interrupt Enable R/W 0 3 EP3 Interrupt Enable R/W 0 10 Reserved 9 SOF/EOP Interrupt Enable R/W 0 1 EP1 Interrupt Enable R/W 0 8 Reset Interrupt Enable R/W 0 0 EP0 Interrupt Enable R/W 0
0 2 EP2 Interrupt Enable R/W 0
Register Description
The Device n Interrupt Enable register provides control over device related interrupts including eight different endpoint interrupts.
VBUS Interrupt Enable (Bit 15)
the rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Device 1 and is a reserved bit in Device 2.
1: Enable VBUS interrupt 0: Disable VBUS interrupt
The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled, this interrupt triggers on both
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ID Interrupt Enable (Bit 14)
EP5 Interrupt Enable (Bit 5)
The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled, this interrupt triggers on both the rising and falling edge of the OTG ID pin (only supported in Port 1A). This bit is only available for Device 1 and is a reserved bit in Device 2.
1: Enable ID interrupt 0: Disable ID interrupt SOF/EOP Timeout Interrupt Enable (Bit 11)
The SOF/EOP Timeout Interrupt Enable bit enables or disables the SOF/EOP Timeout Interrupt. When enabled this interrupt triggers when the USB host fails to send a SOF or EOP packet within the time period specified in the Device n SOF/EOP Count register. In addition, the Device n Frame register counts the number of times the SOF/EOP Timeout Interrupt triggers between receiving SOF/EOPs.
1: SOF/EOP timeout occurred 0: SOF/EOP timeout did not occur SOF/EOP Interrupt Enable (Bit 9)
The EP5 Interrupt Enable bit enables or disables endpoint five (EP5) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt. 1: Enable EP5 Transaction Done interrupt 0: Disable EP5 Transaction Done interrupt
EP4 Interrupt Enable (Bit 4)
The SOF/EOP Interrupt Enable bit enables or disables the SOF/EOP received interrupt.
1: Enable SOF/EOP received interrupt 0: Disable SOF/EOP received interrupt Reset Interrupt Enable (Bit 8)
The EP4 Interrupt Enable bit enables or disables endpoint four (EP4) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt. 1: Enable EP4 Transaction Done interrupt 0: Disable EP4 Transaction Done interrupt
EP3 Interrupt Enable (Bit 3)
The Reset Interrupt Enable bit enables or disables the USB Reset Detected interrupt
1: Enable USB Reset Detected interrupt 0: Disable USB Reset Detected interrupt EP7 Interrupt Enable (Bit 7)
The EP3 Interrupt Enable bit enables or disables endpoint three (EP3) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt. 1: Enable EP3 Transaction Done interrupt 0: Disable EP3 Transaction Done interrupt
EP2 Interrupt Enable (Bit 2)
The EP7 Interrupt Enable bit enables or disables endpoint seven (EP7) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt.
1: Enable EP7 Transaction Done interrupt 0: Disable EP7 Transaction Done interrupt EP6 Interrupt Enable (Bit 6)
The EP2 Interrupt Enable bit enables or disables endpoint two (EP2) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt. 1: Enable EP2 Transaction Done interrupt 0: Disable EP2 Transaction Done interrupt
EP1 Interrupt Enable (Bit 1)
The EP6 Interrupt Enable bit enables or disables endpoint six (EP6) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt.
1: Enable EP6 Transaction Done interrupt 0: Disable EP6 Transaction Done interrupt
The EP1 Interrupt Enable bit enables or disables endpoint one (EP1) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt. 1: Enable EP1 Transaction Done interrupt 0: Disable EP1 Transaction Done interrupt Page 44 of 98
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EP0 Interrupt Enable (Bit 0)
The EP0 Interrupt Enable bit enables or disables endpoint zero (EP0) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK
Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses trigger this interrupt.
1: Enable EP0 Transaction Done interrupt 0: Disable EP0 Transaction Done interrupt Reserved
Write all reserved bits with '0'.
Device n Address Register [W] * Device 1 Address Register 0xC08E * Device 2 Address Register 0xC0AE Figure 45. Device n Address Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 0 7 ...Reserved 0 W 0 W 0 W 0 0 6 0 5 0 4 15 14 13 12 Reserved... 0 3 Address W 0 W 0 W 0 W 0 0 2 0 1 0 0 11 10 9 8
Register Description
Address (Bits [6:0])
The Device n Address register holds the device address assigned by the host. This register initializes to the default address 0 at reset but must be updated by firmware when the host assigns a new address. Only USB data sent to the address contained in this register gets a respond--all others are ignored.
Device n Status Register [R/W] * Device 1 Status Register 0xC090 * Device 2 Status Register 0xC0B0
The Address field contains the USB address of the device assigned by the host.
Reserved
Write all reserved bits with '0'.
Figure 46. Device n Status Register
Bit # 15 VBUS Interrupt Flag R/W X 7 EP7 Interrupt Flag R/W X 14 ID Interrupt Flag R/W X 6 EP6 Interrupt Flag R/W X X 5 EP5 Interrupt Flag R/W X X 4 EP4 Interrupt Flag R/W X 13 12 Reserved 11 10 9 8 SOF/EOP Reset Interrupt Interrupt Flag Flag X 3 EP3 Interrupt Flag R/W X X 2 EP2 Interrupt Flag R/W X R/W X 1 EP1 Interrupt Flag R/W X R/W X 0 EP0 Interrupt Flag R/W X
Field Read/Write Default Bit # Field Read/Write Default
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Register Description
The Device n Status register provides status information for device operation. Pending interrupts can be cleared by writing a `1' to the corresponding bit. This register can be accessed by the HPI interface.
VBUS Interrupt Flag (Bit 15)
Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1: Interrupt triggered 0: Interrupt did not trigger EP5 Interrupt Flag (Bit 5)
The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Device 1 and is a reserved bit in Device 2.
1: Interrupt triggered 0: Interrupt did not trigger ID Interrupt Flag (Bit 14)
The EP5 Interrupt Flag bit indicates if the endpoint five (EP5) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1: Interrupt triggered 0: Interrupt did not trigger EP4 Interrupt Flag (Bit 4)
The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin. This bit is only available for Device 1 and is a reserved bit in Device 2.
1: Interrupt triggered 0: Interrupt did not trigger SOF/EOP Interrupt Flag (Bit 9)
The SOF/EOP Interrupt Flag bit indicates if the SOF/EOP received interrupt triggered.
1: Interrupt triggered 0: Interrupt did not trigger Reset Interrupt Flag (Bit 8)
The EP4 Interrupt Flag bit indicates if the endpoint four (EP4) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1: Interrupt triggered 0: Interrupt did not trigger EP3 Interrupt Flag (Bit 3)
The Reset Interrupt Flag bit indicates if the USB Reset Detected interrupt triggered.
1: Interrupt triggered 0: Interrupt did not trigger EP7 Interrupt Flag (Bit 7)
The EP3 Interrupt Flag bit indicates if the endpoint three (EP3) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1: Interrupt triggered 0: Interrupt did not trigger EP2 Interrupt Flag (Bit 2)
The EP7 Interrupt Flag bit indicates if the endpoint seven (EP7) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1: Interrupt triggered 0: Interrupt did not trigger EP6 Interrupt Flag (Bit 6)
The EP2 Interrupt Flag bit indicates if the endpoint two (EP2) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1: Interrupt triggered 0: Interrupt did not trigger EP1 Interrupt Flag (Bit 1)
The EP6 Interrupt Flag bit indicates if the endpoint six (EP6) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt
The EP1 Interrupt Flag bit indicates if the endpoint one (EP1) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device's supplied EP: Page 46 of 98
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send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1: Interrupt triggered 0: Interrupt did not trigger EP0 Interrupt Flag (Bit 0)
events occur in a transaction for the device's supplied EP: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, if the NAK Interrupt Enable bit in the Device n Endpoint Control register is set, this interrupt also triggers when the device NAKs host requests.
1: Interrupt triggered 0: Interrupt did not trigger Reserved
The EP0 Interrupt Flag bit indicates if the endpoint zero (EP0) Transaction Done interrupt triggered. An EPx Transaction Done interrupt triggers when any of the following responses or
Write all reserved bits with '0'.
Device n Frame Number Register [R] * Device 1 Frame Number Register 0xC092 * Device 2 Frame Number Register 0xC0B2 Figure 47. Device n Frame Number Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R 0 R 0 R 0 R 0 15 SOF/EOP Timeout Flag R 0 7 R 0 6 14 13 SOF/EOP Timeout Interrupt Counter R 0 5 R 0 4 ...Frame R 0 R 0 R 0 R 0 12 11 Reserved 0 3 R 0 2 10 9 Frame... R 0 1 R 0 0 8
Register Description
SOF/EOP Timeout Interrupt Counter (Bits [14:12])
The Device n Frame Number register is a read only register that contains the Frame number of the last SOF packet received. This register also contains a count of SOF/EOP Timeout occurrences.
SOF/EOP Timeout Flag (Bit 15)
The SOF/EOP Timeout Interrupt Counter field increments by 1 from 0 to 7 for each SOF/EOP Timeout Interrupt. This field resets to 0 when a SOF/EOP is received. This field is only updated when the SOF/EOP Timeout Interrupt Enable bit in the Device n Interrupt Enable register is set.
Frame (Bits [10:0])
The SOF/EOP Timeout Flag bit indicates when an SOF/EOP Timeout Interrupt occurs.
1: An SOF/EOP Timeout interrupt occurred 0: An SOF/EOP Timeout interrupt did not occur
The Frame field contains the frame number from the last received SOF packet in full-speed mode. This field no function for low-speed mode. If a SOF Timeout occurs, this field contains the last received Frame number.
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Device n SOF/EOP Count Register [W] * Device 1 SOF/EOP Count Register 0xC094 * Device 2 SOF/EOP Count Register 0xC0B4 Figure 48. Device n SOF/EOP Count Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R 1 R 1 R 1 R 0 0 7 15 Reserved 0 6 R 1 5 R 0 4 ...Count R 0 R 0 R 0 R 0 R 1 3 14 13 12 11 Count... R 1 2 R 1 1 R 0 0 10 9 8
Register Description
Reserved
The Device n SOF/EOP Count register is written with the time expected between receiving a SOF/EOP. If the SOF/EOP counter expires before an SOF/EOP is received, an SOF/EOP Timeout Interrupt can be generated. The SOF/EOP Timeout Interrupt Enable and SOF/EOP Timeout Interrupt Flag are located in the Device n Interrupt Enable and Status registers respectively. Set the SOF/EOP count slightly greater than the expected SOF/EOP interval. The SOF/EOP counter decrements at a 12 MHz rate. Therefore, in the case of an expected 1 ms SOF/EOP interval, the SOF/EOP count is set slightly greater than 0x2EE0.
Count (Bits [13:0])
Write all reserved bits with '0'.
OTG Control Registers
There is one register dedicated for On-The-Go operation. This register is covered in this section and summarized in Table 36.
Table 36. OTG Register Register Name Address R/W
OTG Control Register
C098H
R/W
The Count field contains the current value of the SOF/EOP down counter. At power up and reset, this value is set to 0x2EE0 and for expected 1 ms SOF/EOP intervals, this SOF/EOP count is increased slightly.
OTG Control Register [0xC098] [R/W] Figure 49. OTG Control Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 0 7 D+ Pull-down Enable R/W 0 0 15 14 13 VBUS Pull-up Enable R/W 0 6 D- Pull-down Enable R/W 0 0 12 Receive Disable R/W 0 5 4 Reserved 0 0 11 10 9 D+ Pull-up Enable R/W 0 2 OTG Data Status R X 1 ID Status R X 8 D- Pull-up Enable R/W 0 0 VBUS Valid Flag R X Reserved Charge Pump VBUS Enable Discharge Enable R/W 0 3 R/W 0
Register Description
VBUS Pull-up Enable (Bit 13)
The OTG Control register allows control and monitoring over the OTG port on Port1A. Note that the D pull up and pull down bits override the setting in the USB 0 Control register for this port.
The VBUS Pull-up Enable bit enables or disables a 500 ohm pull up resistor onto OTG VBus.
1: 500 ohm pull up resistor enabled 0: 500 ohm pull up resistor disabled
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Receive Disable (Bit 12)
OTG Data Status (Bit 2)
The Receive Disable bit enables or powers down (disables) the OTG receiver section.
1: OTG receiver powered down and disabled 0: OTG receiver enabled Charge Pump Enable (Bit 11)
The OTG Data Status bit is a read only bit and indicates the TTL logic state of the OTG VBus pin.
1: OTG VBus is greater then 2.4V 0: OTG VBus is less then 0.8V ID Status (Bit 1)
The Charge Pump Enable bit enables or disables the OTG VBus charge pump.
1: OTG VBus charge pump enabled 0: OTG VBus charge pump disabled VBUS Discharge Enable (Bit 10)
The ID Status bit is a read only bit that indicates the state of the OTG ID pin on Port A.
1: OTG ID Pin is not connected directly to ground (>10K ohm) 0: OTG ID Pin is connected directly ground (< 10 ohm) VBUS Valid Flag (Bit 0)
The VBUS Discharge Enable bit enables or disables a 2K ohm discharge pull down resistor onto OTG VBus.
1: 2K ohm pull down resistor enabled 0: 2K ohm pull down resistor disabled D+ Pull-up Enable (Bit 9)
The VBUS Valid Flag bit indicates whether OTG VBus is greater then 4.4V. After turning on VBUS, firmware must wait at least 10 s before this reading this bit.
1: OTG VBus is greater then 4.4V 0: OTG VBus is less then 4.4V Reserved
The D+ Pull-up Enable bit enables or disables a pull up resistor on the OTG D+ data line.
1: OTG D+ dataline pull up resistor enabled 0: OTG D+ dataline pull up resistor disabled D- Pull-up Enable (Bit 8)
Write all reserved bits with '0'.
GPIO Registers
The D- Pull-up Enable bit enables or disables a pull up resistor on the OTG D- data line.
1: OTG D- dataline pull up resistor enabled 0: OTG D- dataline pull up resistor disabled D+ Pull-down Enable (Bit 7)
There are seven registers dedicated for GPIO operations. These seven registers are covered in this section and summarized in Table 37.
Table 37. GPIO Registers Register Name Address R/W
GPIO Control Register GPIO0 Output Data Register GPIO0 Input Data Register GPIO0 Direction Register GPIO1 Output Data Register GPIO1 Input Data Register GPIO1 Direction Register
0xC006 0xC01E 0xC020 0xC022 0xC024 0xC026 0xC028
R/W R/W R R/W R/W R R/W
The D+ Pull-down Enable bit enables or disables a pull down resistor on the OTG D+ data line.
1: OTG D+ dataline pull down resistor enabled 0: OTG D+ dataline pull down resistor disabled D- Pull-down Enable (Bit 6)
The D- Pull-down Enable bit enables or disables a pull down resistor on the OTG D- data line.
1: OTG D- dataline pull down resistor enabled 0: OTG D- dataline pull down resistor disabled
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GPIO Control Register [0xC006] [R/W] Figure 50. GPIO Control Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 15 Write Protect Enable R/W 0 7 HSS Enable R/W 0 14 UD R/W 0 6 HSS XD Enable R/W 0 0 5 SPI Enable R/W 0 13 Reserved 0 4 SPI XD Enable R/W 0 12 11 SAS Enable R/W 0 3 Interrupt 1 Polarity Select R/W 0 R/W 0 2 Interrupt 1 Enable R/W 0 10 9 Mode Select R/W 0 1 Interrupt 0 Polarity Select R/W 0 R/W 0 0 Interrupt 0 Enable R/W 0 8
Register Description
HSS Enable (Bit 7)
The GPIO Control register configures the GPIO pins for various interface options. It also controls the polarity of the GPIO interrupt on IRQ1 (GPIO25) and IRQ0 (GPIO24).
Write Protect Enable (Bit 15)
The Write Protect Enable bit enables or disables the GPIO write protect. When Write Protect is enabled, the GPIO Mode Select [15:8] field is read only until a chip reset. 1: Enable Write Protect 0: Disable Write Protect
UD (Bit 14)
The HSS Enable bit routes HSS to GPIO[26, 18:16]. If the HSS XD Enable bit is set, it overrides this bit and HSS is routed to XD[15:12]. 1: HSS is routed to GPIO 0: HSS is not routed to GPIOs. GPIO[26, 18:16] are free for other purposes
HSS XD Enable (Bit 6)
The UD bit routes the Host/Device 1A Port's transmitter enable status to GPIO[30]. This is for use with an external ESD protection circuit when needed. 1: Route the signal to GPIO[30] 0: Do not route the signal to GPIO[30]
SAS Enable (Bit 11)
The HSS XD Enable bit routes HSS to XD[15:12] (external memory data bus). This bit overrides the HSS Enable bit. 1: HSS is routed to XD[15:12] 0: HSS is not routed to XD[15:12]
SPI Enable (Bit 5)
The SAS Enable bit, when in SPI mode, reroutes the SPI port SPI_nSSI pin to GPIO[15] rather then GPIO[9] or XD[9] (per SG/SX). 1: Reroute SPI_nss to GPIO[30] 0: Leave SPI_nss on GPIO[9]
Mode Select (Bits [10:8])
The SPI Enable bit routes SPI to GPIO[11:8]. If the SAS Enable bit is set, it overrides the SPI Enable and routes SPI_nSSI to GPIO15. If the SPI XD Enable bit is set, it overrides both bits and the SPI is routed to XD[11:8] (external memory data bus). 1: SPI is routed to GPIO[11:8] 0: SPI is not routed to GPIO[11:8]. GPIO[11:8] are free for other purposes
SPI XD Enable (Bit 4)
The Mode Select field selects how GPIO[15:0] and GPIO[24:19] are used as defined in Table 38.
Table 38. Mode Select Definition Mode Select GPIO Configuration [10:8] 111 Reserved 110 SCAN -- (HW) Scan diagnostic. For production test only. Not for normal operation 101 HPI -- Host Port Interface 100 IDE -- Integrated Drive Electronics or 011 Reserved 010 Reserved 001 Reserved 000 GPIO -- General Purpose Input Output
The SPI XD Enable bit routes SPI to XD[11:8] (external memory data bus). This bit overrides the SPI Enable bit. 1: SPI is routed to XD[11:8] 0: SPI is not routed to XD[11:8]
Interrupt 1 Polarity Select (Bit 3)
The Interrupt 1 Polarity Select bit selects the polarity for IRQ1. 1: Sets IRQ1 to rising edge 0: Sets IRQ1 to falling edge
Interrupt 1 Enable (Bit 2)
The Interrupt 1 Enable bit enables or disables IRQ1. The GPIO bit on the interrupt Enable register must also be set in order for this for this interrupt to be enabled. 1: Enable IRQ1 0: Disable IRQ1 Page 50 of 98
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Interrupt 0 Polarity Select (Bit 1)
Reserved
The Interrupt 0 Polarity Select bit selects the polarity for IRQ0. 1: Sets IRQ0 to rising edge 0: Sets IRQ0 to falling edge
Interrupt 0 Enable (Bit 0)
Write all reserved bits with '0'.
The Interrupt 0 Enable bit enables or disables IRQ0. The GPIO bit on the interrupt Enable register must also be set in order for this for this interrupt to be enabled. 1: Enable IRQ0 0: Disable IRQ0
GPIO n Output Data Register [R/W] * GPIO 0 Output Data Register 0xC01E * GPIO 1 Output Data Register 0xC024 Figure 51. GPIO n Output Data Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 23/7 R/W 0 22/6 R/W 0 21/5 R/W 0 20/4 ...Data R/W 0 R/W 0 R/W 0 R/W 0 31/15 30/14 29/13 28/12 Data... R/W 0 19/3 R/W 0 18/2 R/W 0 17/1 R/W 0 16/0 27/11 26/10 25/9 24/8
Register Description
Data (Bits [15:0])
The GPIO n Output Data register controls the output data of the GPIO pins. The GPIO 0 Output Data register controls GPIO15 to GPIO0 while the GPIO 1 Output Data register controls GPIO31 to GPIO16. When read, this register reads back the last data written, not the data on pins configured as inputs (see Input Data Register).
GPIO n Input Data Register [R] * GPIO 0 Input Data Register 0xC020 * GPIO 1 Input Data Register 0xC026
The Data field[15:0] writes to the corresponding GPIO 15-0 or GPIO31-16 pins as output data.
Figure 52. GPIO n Input Data Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R 0 R 0 R 0 R 0 R 0 23/7 R 0 22/6 R 0 21//5 R 0 20/4 ...Data R 0 R 0 R 0 R 0 31/15 30/14 29/13 28/12 Data... R 0 19/3 R 0 18/2 R 0 17/1 R 0 16/0 27/11 26/10 25/9 24/8
Register Description
Data (Bits [15:0])
The GPIO n Input Data register reads the input data of the GPIO pins. The GPIO 0 Input Data register reads from GPIO15 to GPIO0 while the GPIO 1 Input Data register reads from GPIO31 to GPIO16. Document #: 38-08015 Rev. *H
The Data field[15:0] contains the voltage values on the corresponding GPIO15-0 or GPIO31-16 input pins.
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GPIO n Direction Register [R/W] * GPIO 0 Direction Register 0xC022 * GPIO 1 Direction Register 0xC028 Figure 53. GPIO n Direction Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 23/7 R/W 0 22/6 R/W 0 21/5 31/15 30/14 29/13 28/12 R/W 0 20/4 R/W 0 27/11 R/W 0 19/3 R/W 0 26/10 R/W 0 18/2 R/W 0 25/9 R/W 0 17/1 R/W 0 24/8 R/W 0 16/0 R/W 0 Direction Select...
...Direction Select
Register Description
IDE Registers
The GPIO n Direction register controls the direction of the GPIO data pins (input/output). The GPIO 0 Direction register controls GPIO15 to GPIO0 while the GPIO 1 Direction register controls GPIO31 to GPIO16.
Direction Select (Bits [15:0])
In addition to the standard IDE PIO Port registers, there are four registers dedicated to IDE operation. These registers are covered in this section and summarized in Table 39.
Table 39. IDE Registers Register Name Address R/W
The Direction Select field[15:0] configures the corresponding GPIO15-0 or GPIO31-16 pins as either input or output. When any bit of this register is set to `1', the corresponding GPIO data pin becomes an output. When any bit of this register is set to `0', the corresponding GPIO data pin becomes an input.
IDE Mode Register IDE Start Address Register IDE Stop Address Register IDE Control Register IDE PIO Port Registers
0xC048 0xC04A 0xC04C 0xC04E 0xC050-0xC06F
R/W R/W R/W R/W R/W
IDE Mode Register [0xC048] [R/ W] Figure 54. IDE Mode Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 0 7 0 6 0 5 ...Reserved 0 0 R/W 0 R/W 0 0 4 15 14 13 12 Reserved... 0 3 0 2 0 1 Mode Select R/W 0 R/W 0 0 0 11 10 9 8
Register Description
Mode Select (Bits [2:0])
The IDE Mode register allows the selection of IDE PIO Modes 0, 1, 2, 3, or 4. The default setting is zero which means IDE PIO Mode 0.
The Mode Select field sets PIO Mode 0 to 4 in IDE mode. Refer to Table 40 on page 53 for a definition of this field.
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Table 40. Mode Select Definition Mode Select [2:0] 000 001 010 011 100 101 110 111 Reserved Mode IDE PIO Mode 0 IDE PIO Mode 1 IDE PIO Mode 2 IDE PIO Mode 3 IDE PIO Mode 4 Reserved Reserved Disable IDE port operations
Write all reserved bits with '0'.
IDE Start Address Register [0xC04A] [R/W] Figure 55. IDE Start Address Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8
Register Description
The IDE Start Address register holds the start address for an IDE block transfer. This register is byte addressed and IDE block transfers are 16-bit words, therefore the LSB of the start address is ignored. Block transfers begin at IDE Start Address and end with the final word at IDE Stop Address. When IDE
Address (Bits [15:0])
Start Address equals IDE Stop Address, the block transfer moves one word of data. The hardware keeps an internal memory address counter. The two MSBs of the addresses are not modified by the address counter. Therefore, the IDE Start Address and IDE Stop Address must reside within the same 16K byte block.
The Address field sets the start address for an IDE block transfer.
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IDE Stop Address Register [0xC04C] [R/W] Figure 56. IDE Stop Address Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8
Register Description
The IDE Stop Address register holds the stop address for an IDE block transfer. This register is byte addressed and IDE block transfers are 16-bit words, therefore the LSB of the stop address is ignored. Block transfers begin at IDE Start Address and end with the final word at IDE Stop Address. When IDE Start Address equals IDE Stop Address, the block transfer moves one word of data.
IDE Control Register [0xC04E] [R/W]
The hardware keeps an internal memory address counter. The two MSBs of the addresses are not modified by the address counter. Therefore the IDE Start Address and IDE Stop Address must reside within the same 16K byte block.
Address (Bits [15:0])
The Address field sets the stop address for an IDE block transfer.
Figure 57. IDE Control Register
Bit # Field Read/Write Default Bit # 0 7 0 6 ...Reserved Field Read/Write Default 0 0 0 0 R/W 0 0 5 0 4 15 14 13 12 Reserved... 0 3 Direction Select 0 2 IDE Interrupt Enable R/W 0 0 1 Done Flag R/W 0 0 0 IDE Enable R/W 0 11 10 9 8
Register Description
Done Flag (Bit 1)
The IDE Control register controls block transfers in IDE mode.
Direction Select (Bit 3)
The Direction Select bit sets the block mode transfer direction.
1: Data is written to the external device 0: Data is read from the external device IDE Interrupt Enable (Bit 2)
The Done Flag bit is automatically set to `1' by hardware when a block transfer is complete. The CPU clears this bit by writing a `0' to it. When IDE Interrupt Enable is set this bit generates the signal for the cpuide_intr interrupt.
1: Block transfer is complete 0: Clears IDE Done Flag IDE Enable (Bit 0)
The IDE Interrupt Enable bit enables or disables the block transfer done interrupt. When enabled, the Done Flag is sent to the CPU as cpuide_intr interrupt. When disabled, the cpuide_intr is set LOW.
1: Enable block transfer done interrupt 0: Disable block transfer done interrupt
The IDE Enable bit starts a block transfer. It is reset to `0' when the block transfer is complete
1: Start block transfer 0: Block transfer complete Reserved
Write all reserved bits with '0'.
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IDE PIO Port Registers [0xC050 - 0xC06F] [R/W]
All IDE PIO Port registers [0xC050 - 0xC06F] in Table 41 are defined in detail in the Information Technology-AT Attachment -4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. The table Address column denotes the CY7C67300 register address for the corresponding
Table 41. IDE PIO Port Registers Address ATA/ATAPI Register
ATA/ATAPI register. The IDE_nCS[1:0] field defines the ATA interface CS addressing bits and the IDE_A[2:0] field define the ATA interface address bits. The combination of IDE_nCS and IDE_A are the ATA interface register address.
IDE_nCS[1:0]
IDE_A[2:0]
0xC050 0xC052 0xC054 0xC056 0xC058 0xC05A 0xC05C 0xC05E 0xC060 0xC062 0xC064 0xC066 0xC068 0xC06A 0xC06C 0xC06E
HSS Registers
DATA Register Read: Error Register Write: Feature Register Sector Count Register Sector Number Register Cylinder Low Register Cylinder High Register Device/Head Register Read: Status Register Write: Command Register Not Defined Not Defined Not Defined Not Defined Not Defined Not Defined Read: Alternate Status Register Write: Device Control Register Not Defined
`10' `10' `10' `10' `10' `10' `10' `10' `01' `01' `01' `01' `01' `01' `01' `01'
`000' `001' `010' `011' `100' `101' `110' `111' `000' `001' `010' `011' `100' `101' `110' `111'
There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized in Table 42.
Table 42. HSS Registers Register Name Address R/W
HSS Control Register HSS Baud Rate Register HSS Transmit Gap Register HSS Data Register HSS Receive Address Register HSS Receive Length Register HSS Transmit Address Register HSS Transmit Length Register
0xC070 0xC072 0xC074 0xC076 0xC078 0xC07A 0xC07C 0xC07E
R/W R/W R/W R/W R/W R/W R/W R/W
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HSS Control Register [0xC070] [R/W] Figure 58. HSS Control Register
Bit # 15 HSS Enable Field Read/Write Default Bit # R/W 0 7 14 RTS Polarity Select R/W 0 6 13 CTS Polarity Select R/W 0 5 One Stop Bit R/W 0 12 XOFF 11 XOFF Enable R/W 0 3 Packet Mode Select R/W 0 10 CTS Enable R/W 0 2 Receive Overflow Flag R/W 0 9 Receive Interrupt Enable R/W 0 1 Receive Packet Ready Flag R 0 8 Done Interrupt Enable R/W 0 0 Receive Ready Flag R 0
R 0 4 Transmit Ready R 0
Field Read/Write Default
Transmit Receive Done Interrupt Done Interrupt Enable Enable R/W 0 R/W 0
Register Description
Receive Interrupt Enable (Bit 9)
The HSS Control register provides high level status and control over the HSS port.
HSS Enable (Bit 15)
The Receive Interrupt Enable bit enables or disables the Receive Ready and Receive Packet Ready interrupts.
1: Enable the Receive Ready and Receive Packet Ready interrupts 0: Disable the Receive Ready and Receive Packet Ready interrupts Done Interrupt Enable (Bit 8)
The HSS Enable bit enables or disables HSS operation.
1: Enables HSS operation 0: Disables HSS operation RTS Polarity Select (Bit 14)
The RTS Polarity Select bit selects the polarity of RTS.
1: RTS is true when LOW 0: RTS is true when HIGH CTS Polarity Select (Bit 13)
The Done Interrupt Enable bit enables or disables the Transmit Done and Receive Done interrupts.
1: Enable the Transmit Done and Receive Done interrupts 0: Disable the Transmit Done and Receive Done interrupts Transmit Done Interrupt Flag (Bit 7)
The CTS Polarity Select bit selects the polarity of CTS.
1: CTS is true when LOW 0: CTS is true when HIGH XOFF (Bit 12)
The Transmit Done Interrupt Flag bit indicates the status of the Transmit Done Interrupt. It sets when a block transmit is finished. To clear the interrupt, write a `1' to this bit.
1: Interrupt triggered 0: Interrupt did not trigger Receive Done Interrupt Flag (Bit 6)
The XOFF bit is a read only bit that indicates if an XOFF was received. This bit is automatically cleared when an XON is received.
1: XOFF received 0: XON received XOFF Enable (Bit 11)
The Receive Done Interrupt Flag bit indicates the status of the Receive Done Interrupt. It sets when a block transmit is finished. To clear the interrupt, write a `1' to this bit.
1: Interrupt triggered 0: Interrupt did not trigger One Stop Bit (Bit 5)
The XOFF Enable bit enables or disables XON/XOFF software handshaking.
1: Enable XON/XOFF software handshaking 0: Disable XON/XOFF software handshaking CTS Enable (Bit 10)
The One Stop Bit bit selects between one and two stop bits for transmit byte mode. In receive mode, the number of stop bits may vary and does not need to be fixed.
1: One stop bit 0: Two stop bits
The CTS Enable bit enables or disables CTS/RTS hardware handshaking.
1: Enable CTS/RTS hardware handshaking 0: Disable CTS/RTS hardware handshaking
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Transmit Ready (Bit 4)
1: Overflow occurred 0: Overflow did not occur Receive Packet Ready Flag (Bit 1)
The Transmit Ready bit is a read only bit that indicates if the HSS Transmit FIFO is ready for the CPU to load new data for transmission.
1: HSS transmit FIFO ready for loading 0: HSS transmit FIFO not ready for loading Packet Mode Select (Bit 3)
The Receive Packet Ready Flag bit is a read only bit that indicates if the HSS receive FIFO is full with eight bytes or not.
1: HSS receive FIFO is full 0: HSS receive FIFO is not full Receive Ready Flag (Bit 0)
The Packet Mode Select bit selects between Receive Packet Ready and Receive Ready as the interrupt source for the RxIntr interrupt.
1: Selects Receive Packet Ready as the source 0: Selects Receive Ready as the source Receive Overflow Flag (Bit 2)
The Receive Ready Flag is a read only bit that indicates if the HSS receive FIFO is empty or not.
1: HSS receive FIFO is not empty (one or more bytes is reading for reading) 0: HSS receive FIFO is empty
The Receive Overflow Flag bit indicates if the Receive FIFO overflowed when set. This flag can be cleared by writing a `1' to this bit.
HSS Baud Rate Register [0xC072] [R/W] Figure 59. HSS Baud Rate Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 1 0 7 15 14 Reserved 0 6 0 5 R/W 0 4 ...Baud R/W 0 R/W 1 R/W 1 R/W 1 R/W 0 3 13 12 11 10 Baud... R/W 0 2 R/W 0 1 R/W 0 0 9 8
Register Description
The HSS Baud Rate register sets the HSS Baud Rate. At reset, the default value is 0x0017 which sets the baud rate to 2.0 MHz.
Baud (Bits [12:0])
The Baud field is the baud rate divisor minus one, in units of 1/48 MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts a constraint on the Baud Value as follows: (24 - 1) Baud (5000 - 1)
Reserved
Write all reserved bits with '0'.
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HSS Transmit Gap Register [0xC074] [R/W] Figure 60. HSS Transmit Gap Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 0 7 0 6 0 5 0 4 R/W 0 15 14 13 12 Reserved 0 3 R/W 1 0 2 R/W 0 0 1 R/W 0 0 0 R/W 1 11 10 9 8
Transmit Gap Select
Register Description
Reserved
The HSS Transmit Gap register is only valid in block transmit mode. It allows for a programmable number of stop bits to be inserted, thus overwriting the One Stop Bit in the HSS Control register. The default reset value of this register is 0x0009, equivalent to two stop bits.
Transmit Gap Select (Bits [7:0])
Write all reserved bits with '0'.
The Transmit Gap Select field sets the inactive time between transmitted bytes. The inactive time = (Transmit Gap Select -7) * bit time. Therefore a Transmit Gap Select Value of 8 is equal to having one Stop bit.
HSS Data Register [0xC076] [R/W] Figure 61. HSS Data Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W X R/W X R/W X R/W X X 7 X 6 X 5 X 4 Data R/W X R/W X R/W X R/W X 15 14 13 12 Reserved X 3 X 2 X 1 X 0 11 10 9 8
Register Description
Data (Bits [7:0])
The HSS Data register contains data received on the HSS port (not for block receive mode) when read. This receive data is valid when the Receive Ready bit of the HSS Control register is set to `1'. Writing to this register initiates a single byte transfer of data. The Transmit Ready Flag in the HSS Control register must read `1' before writing to this register (this avoids disrupting the previous/current transmission).
The Data field contains the data received or to be transmitted on the HSS port.
Reserved
Write all reserved bits with '0'.
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HSS Receive Address Register [0xC078] [R/W] Figure 62. HSS Receive Address Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8
Register Description
Address (Bits [15:0])
The HSS Receive Address register is used as the base pointer address for the next HSS block receive transfer.
The Address field sets the base pointer address for the next HSS block receive transfer.
HSS Receive Counter Register [0xC07A] [R/W] Figure 63. HSS Receive Counter Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 0 5 15 14 13 Reserved 0 4 ...Counter R/W 0 R/W 0 R/W 0 R/W 0 0 3 0 2 R/W 0 1 12 11 10 9 Counter... R/W 0 0 8
Register Description
Counter (Bits [9:0])
The HSS Receive Counter register designates the block byte length for the next HSS receive transfer. Load this register with the word count minus one to start the block receive transfer. As each byte is received this register value is decremented. When read, this register indicates the remaining length of the transfer.
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When the transfer is complete this register returns 0x03FF until reloaded.
Reserved
Write all reserved bits with '0'.
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HSS Transmit Address Register [0xC07C] [R/W] Figure 64. HSS Transmit Address Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8
Register Description
Address (Bits [15:0])
The HSS Transmit Address register is used as the base pointer address for the next HSS block transmit transfer.
The Address field sets the base pointer address for the next HSS block transmit transfer.
HSS Transmit Counter Register [0xC07E] [R/W] Figure 65. HSS Transmit Counter Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 0 5 15 14 13 Reserved 0 4 ...Counter R/W 0 R/W 0 R/W 0 R/W 0 0 3 0 2 R/W 0 1 12 11 10 9 Counter... R/W 0 0 8
Register Description
Counter (Bits [9:0])
The HSS Transmit Counter register designates the block byte length for the next HSS transmit transfer. Load this register with the word count minus one to start the block transmit transfer. As each byte is transmitted this register value is decremented. When read, this register indicates the remaining length of the transfer.
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When the transfer is complete this register returns 0x03FF until reloaded.
Reserved
Write all reserved bits with '0'.
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HPI Registers
Table 43. HPI Registers Register Name HPI Breakpoint Register Interrupt Routing Register SIE1msg Register SIE2msg Register HPI Mailbox Register Address 0x0140 0x0142 0x0144 0x0148 0xC0C6 R/W R R W W R/W
There are five registers dedicated to HPI operation. In addition, there is an HPI status port which can be addressed over HPI. Each of these registers is covered in this section and are summarized in Table 43.
HPI Breakpoint Register [0x0140] [R] Figure 66. HPI Breakpoint Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R 0 R 0 R 0 R 0 R 0 7 R 0 6 R 0 5 R 0 4 ...Address R 0 R 0 R 0 R 0 15 14 13 12 Address... R 0 3 R 0 2 R 0 1 R 0 0 11 10 9 8
Register Description
The HPI Breakpoint register is a special on-chip memory location that the external processor can access using normal HPI memory read/write cycles. This register is read only by the CPU but is read/write by the HPI port. The contents of this register have the same effect as the Breakpoint register [0xC014]. This special Breakpoint register is used by software debuggers that interface through the HPI port instead of the serial port.
Interrupt Routing Register [0x0142] [R]
When the program counter matches the Breakpoint Address, the INT127 interrupt triggers. To clear this interrupt, write a zero a to this register.
Address (Bits [15:0])
The Address field is a 16-bit field containing the breakpoint address.
Figure 67. Interrupt Routing Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 15 VBUS to HPI Enable 0 7 Resume2 to HPI Enable 0 14 ID to HPI Enable 0 6 Resume1 to HPI Enable 0 0 13 12 11 10 9 8 HPI Swap 1 Enable 0 0 HPI Swap 0 Enable 0 SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Enable CPU Enable HPI Enable CPU Enable Enable 0 5 Reserved 0 1 4 0 3 Done2 to HPI Enable 0 1 2 0 1
Done1 to HPI Reset1 to HPI Enable Enable 0 0
Register Description
The Interrupt Routing register allows the HPI port to take over some or all of the SIE interrupts that usually go to the on-chip CPU. This register is read only by the CPU but is read/write by the HPI port. By setting the appropriate bit to `1', the SIE interrupt is routed to the HPI port to become the HPI_INTR signal and also readable in the HPI Status register. The bits in this register select where the interrupts are routed. The
individual interrupt enable is handled in the SIE interrupt enable register.
VBUS to HPI Enable (Bit 15)
The VBUS to HPI Enable bit routes the OTG VBUS interrupt to the HPI port instead of the on-chip CPU. 1: Route signal to HPI port
0: Do not route signal to HPI port
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ID to HPI Enable (Bit 14)
Resume2 to HPI Enable (Bit 7)
The ID to HPI Enable bit routes the OTG ID interrupt to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port 0: Do not route signal to HPI port SOF/EOP2 to HPI Enable (Bit 13)
The Resume2 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port 0: Do not route signal to HPI port Resume1 to HPI Enable (Bit 6)
The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt to the HPI port.
1: Route signal to HPI port 0: Do not route signal to HPI port SOF/EOP2 to CPU Enable (Bit 12)
The Resume1 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port 0: Do not route signal to HPI port Done2 to HPI Enable (Bit 3)
The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2 interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can be routed to both the on-chip CPU and the HPI port, the firmware must ensure only one of the two (CPU, HPI) resets the interrupt.
1: Route signal to CPU 0: Do not route signal to CPU SOF/EOP1 to HPI Enable (Bit 11)
The Done2 to HPI Enable bit routes the Done interrupt for Host/Device 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port 0: Do not route signal to HPI port Done1 to HPI Enable (Bit 2)
The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt to the HPI port.
1: Route signal to HPI port 0: Do not route signal to HPI port SOF/EOP1 to CPU Enable (Bit 10)
The Done1 to HPI Enable bit routes the Done interrupt for Host/Device 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port 0: Do not route signal to HPI port Reset1 to HPI Enable (Bit 1)
The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1 interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt can be routed to both the on-chip CPU and the HPI port, the firmware must ensure only one of the two (CPU, HPI) resets the interrupt.
1: Route signal to CPU 0: Do not route signal to CPU Reset2 to HPI Enable (Bit 9)
The Reset1 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 1 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port 0: Do not route signal to HPI port HPI Swap 0 Enable (Bit 0)
The Reset2 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 2 to the HPI port instead of the on-chip CPU.
1: Route signal to HPI port 0: Do not route signal to HPI port HPI Swap 1 Enable (Bit 8)
Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to `00', the most significant data byte goes to HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to `11', the most significant data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8].
Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to `00', the most significant data byte goes to HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to `11', the most significant data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8].
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SIEXmsg Register [W] * SIE1msg Register 0x0144 * SIE2msg Register 0x0148 Figure 68. SIEXmsg Register
Bit # Field Read/Write Default Bit # Field Read/Write Default W X W X W X W X W X 7 W X 6 W X 5 W X 4 ...Data W X W X W X W X 15 14 13 12 Data... W X 3 W X 2 W X 1 W X 0 11 10 9 8
Register Description
Data (Bits [15:0])
The SIEXmsg register allows an interrupt to be generated on the HPI port. Any write to this register causes the SIEXmsg flag in the HPI Status Port to go high and also causes an interrupt on the HPI_INTR pin. The SIEXmsg flag is automatically cleared when the HPI port reads from this register.
HPI Mailbox Register [0xC0C6] [R/W]
The Data field[15:0] simply needs to have any value written to it to cause SIExmsg flag in the HPI Status Port to go high.
Figure 69. HPI Mailbox Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Message R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Message... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8
Register Description
The HPI Mailbox register provides a common mailbox between the CY7C67300 and the external host processor. If enabled, the HPI Mailbox RX Full interrupt triggers when the external host processor writes to this register. When the CY7C67300 reads this register the HPI Mailbox RX Full interrupt is automatically cleared. If enabled, the HPI Mailbox TX Empty interrupt triggers when the external host processor reads from this register. The HPI Mailbox TX Empty interrupt automatically clears when the CY7C67300 writes to this register.
In addition, when the CY7C67300 writes to this register, the HPI_INTR signal on the HPI port asserts, signaling the external processor that there is data in the mailbox to read. The HPI_INTR signal deasserts when the external host processor reads from this register.
Message (Bits [15:0])
The Message field contains the message that the host processor wrote to the HPI Mailbox register.
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HPI Status Port [] [HPI: R] Figure 70. HPI Status Port
Bit # Field Read/Write Default Bit # Field Read/Write Default 15 VBUS Flag R X 7 Resume2 Flag R X 14 ID Flag R X 6 Resume1 Flag R X 13 Reserved X 5 SIE2msg R X 12 SOF/EOP2 Flag R X 4 SIE1msg R X 11 Reserved X 3 Done2 Flag R X 10 SOF/EOP1 Flag R X 2 Done1 Flag R X 9 Reset2 Flag R X 1 Reset1 Flag R X 8 Mailbox In Flag R X 0 Mailbox Out Flag R X
Register Description
Mailbox In Flag (Bit 8)
The HPI Status Port provides the external host processor with the MailBox status bits plus several SIE status bits. This register is not accessible from the on-chip CPU. The additional SIE status bits are provided to aid external device driver firmware development, and are not recommended for applications that do not have an intimate relationship with the on-chip BIOS. Reading from the HPI Status Port does not result in a CPU HPI interface memory access cycle. The external host may continuously poll this register without degrading the CPU or DMA performance.
VBUS Flag (Bit 15)
The Mailbox In Flag bit is a read only bit that indicates if a message is ready in the incoming mailbox. This interrupt clears when the on-chip CPU reads from the HPI Mailbox register.
1: Interrupt triggered 0: Interrupt did not trigger Resume2 Flag (Bit 7)
The Resume2 Flag bit is a read only bit that indicates if a USB resume interrupt occurs on either Host/Device 2.
1: Interrupt triggered 0: Interrupt did not trigger Resume1 Flag (Bit 6)
The VBUS Flag bit is a read only bit that indicates whether OTG VBus is greater than 4.4V. After turning on VBUS, firmware must wait at least 10 s before this reading this bit.
1: OTG VBus is greater than 4.4V 0: OTG VBus is less than 4.4V ID Flag (Bit 14)
The Resume1 Flag bit is a read only bit that indicates if a USB resume interrupt occurs on either Host/Device 1.
1: Interrupt triggered 0: Interrupt did not trigger SIE2msg (Bit 5)
The ID Flag bit is a read only bit that indicates the state of the OTG ID pin.
SOF/EOP2 Flag (Bit 12)
The SIE2msg Flag bit is a read only bit that indicates if the CY7C67300 CPU wrote to the SIE2msg register. This bit is cleared on an HPI read.
1: The SIE2msg register was written by the CY7C67300 CPU 0: The SIE2msg register was not written by the CY7C67300 CPU SIE1msg (Bit 4)
The SOF/EOP2 Flag bit is a read only bit that indicates if a SOF/EOP interrupt occurs on either Host/Device 2.
1: Interrupt triggered 0: Interrupt did not trigger SOF/EOP1 Flag (Bit 10)
The SOF/EOP1 Flag bit is a read only bit that indicates if a SOF/EOP interrupt occurs on either Host/Device 1.
1: Interrupt triggered 0: Interrupt did not trigger Reset2 Flag (Bit 9)
The SIE1msg Flag bit is a read only bit that indicates if the CY7C67300 CPU wrote to the SIE1msg register. This bit is cleared on an HPI read.
1: The SIE1msg register was written by the CY7C67300 CPU 0: The SIE1msg register was not written by the CY7C67300 CPU Done2 Flag (Bit 3)
The Reset2 Flag bit is a read only bit that indicates if a USB Reset interrupt occurs on either Host/Device 2.
1: Interrupt triggered 0: Interrupt did not trigger
In host mode the Done2 Flag bit is a read only bit that indicates if a host packet done interrupt occurs on Host 2. In device mode this read only bit indicates if an any of the endpoint inter-
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rupts occur on Device 2. Firmware needs to determine which endpoint interrupt occurred.
1: Interrupt triggered 0: Interrupt did not trigger Done1 Flag (Bit 2)
Reset1 Flag (Bit 1)
The Reset1 Flag bit is a read only bit that indicates if a USB Reset interrupt occurs on either Host/Device 1.
1: Interrupt triggered 0: Interrupt did not trigger Mailbox Out Flag (Bit 0)
In host mode the Done 1 Flag bit is a read only bit that indicates if a host packet done interrupt occurs on Host 1. In device mode this read only bit indicates if an any of the endpoint interrupts occur on Device 1. Firmware needs to determine which endpoint interrupt occurred.
1: Interrupt triggered 0: Interrupt did not trigger SPI Registers
The Mailbox Out Flag bit is a read only bit that indicates if a message is ready in the outgoing mailbox. This interrupt clears when the external host reads from the HPI Mailbox register.
1: Interrupt triggered 0: Interrupt did not trigger
There are twelve registers dedicated to SPI operation. Each of these registers is covered in this section and summarized in Table 44.
Table 44. SPI Registers Register Name SPI Configuration Register SPI Control Register SPI Interrupt Enable Register SPI Status Register SPI Interrupt Clear Register SPI CRC Control Register SPI CRC Value SPI Data Register SPI Transmit Address Register SPI Transmit Count Register SPI Receive Address Register SPI Receive Count Register Address R/W
0xC0C8 0xC0CA 0xC0CC 0xC0CE 0xC0D0 0xC0D2 0xC0D4 0xC0D6 0xC0D8 0xC0DA 0xC0DC 0xC0DE
R/W R/W R/W R W R/W R/W R/W R/W R/W R/W R/W
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SPI Configuration Register [0xC0C8] [R/W] Figure 71. SPI Configuration Register
Bit # Field Read/Write Default Bit # 15 3Wire Enable R/W 1 7 Master Active Enable R 0 14 Phase Select R/W 0 6 Master Enable R/W 0 13 SCK Polarity Select R/W 0 5 SS Enable R/W 0 R/W 1 R/W 1 R/W 0 4 0 3 12 11 Scale Select R/W R/W 0 2 SS Delay Select R/W 0 1 10 9 8 Reserved 0 0
Field Read/Write Default
R/W 1
R/W 1
R/W 1
Register Description
The SPI Configuration register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
3Wire Enable (Bit 15)
Table 45. Scale Select Field Definition for SCK Frequency (continued) Scale Select [12:9] 1001 SCK Frequency 500 KHz
The 3Wire Enable bit indicates if the MISO and MOSI data lines are tied together allowing only half duplex operation. 1: MISO and MOSI data lines are tied together 0: Normal MISO and MOSI Full Duplex operation (not tied together)
Phase Select (Bit 14)
1010 1011 1100 1101 1110 1111
Master Active Enable (Bit 7)
375 KHz 250 KHz 375 KHz 250 KHz 375 KHz 250 KHz
The Phase Select bit selects advanced or delayed SCK phase. This field only applies to master mode. 1: Advanced SCK phase 0: Delayed SCK phase
SCK Polarity Select (Bit 13)
This SCK Polarity Select bit selects the polarity of SCK. 1: Positive SCK polarity 0: Negative SCK polarity
Scale Select (Bits [12:9])
The Master Active Enable bit is a read only bit that indicates if the master state machine is active or idle. This field only applies to master mode. 1: Master state machine is active 0: Master state machine is idle
Master Enable (Bit 6)
The Master Enable bit sets the SPI interface to master or slave. This bit is only writable when the Master Active Enable bit reads `0', otherwise the value does not change.
1: Master SPI interface 0: Slave SPI interface SS Enable (Bit 5)
The Scale Select field provides control over the SCK frequency, based on 48 MHz. Refer to Table 45 for a definition of this field. This field only applies to master mode.
Table 45. Scale Select Field Definition for SCK Frequency Scale Select [12:9] 0000 SCK Frequency 12 MHz
The SS Enable bit enables or disables the master SS output.
1: Enable master SS output 0: Disable master SS output (three state master SS output, for single SS line in slave mode) SS Delay Select (Bits [4:0])
0001 0010 0011 0100 0101 0110 0111 1000 Document #: 38-08015 Rev. *H
8 MHz 6 MHz 4 MHz 3 MHz 2 MHz 1.5 MHz 1 MHz 750 KHz
When the SS Delay Select field is set to `00000' this indicates manual mode. In manual mode SS is controlled by the SS Manual bit of the SPI Control register. When the SS Delay Select field is set between `00001' to `11111', this value indicates the count in half bit times of auto transfer delay for: SS low to SCK active, SCK inactive to SS high, SS high time. This field only applies to master mode. Page 66 of 98
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SPI Control Register [0xC0CA] [R/W] Figure 72. SPI Control Register
Bit # 15 SCK Strobe Field Read/Write Default Bit # Field Read/Write Default W 0 7 Transmit Empty R 1 W 0 6 Receive Full R 0 R/W 0 R/W 0 5 R/W 0 4 Transmit Bit Length R/W 0 R/W 0 R/W 0 R/W 0 3 R/W 0 2 R 0 1 Receive Bit Length R/W 0 R/W 0 14 FIFO Init 13 Byte Mode 12 Full Duplex 11 SS Manual 10 Read Enable 9 Transmit Ready 8 Receive Data Ready R 1 0
Register Description
Read Enable (Bit 10)
The SPI Control register controls the SPI port. Fields apply to both master and slave mode unless otherwise noted.
SCK Strobe (Bit 15)
The Read Enable bit initiates a read phase for a master mode transfer or sets the slave to receive (in slave mode).
1: Initiates a read phase for a master transfer or sets a slave to receive. In master mode this bit is sticky and remains set until the read transfer begins. 0: Initiates the write phase for slave operation Transmit Ready (Bit 9)
The SCK Strobe bit starts the SCK strobe at the selected frequency and polarity (set in the SPI Configuration register), but not phase. This bit feature can only be enabled when in master mode and must be during a period of inactivity. This bit is self clearing.
1: SCK Strobe Enable 0: No Function FIFO Init (Bit 14)
The Transmit Ready bit is a read only bit that indicates if the transmit port is ready to empty and ready to be written.
1: Ready for data to be written to the port. The transmit FIFO is not full. 0: Not ready for data to be written to the port Receive Data Ready (Bit 8)
The FIFO Init bit initializes the FIFO and clears the FIFO Error Status bit. This bit is self clearing.
1: FIFO Init Enable 0: No Function Byte Mode (Bit 13)
The Receive Data Ready bit is a read only bit that indicates if the receive port has data ready.
1: Receive port has data ready to read 0: Receive port does not have data ready Transmit Empty (Bit 7)
The Byte Mode bit selects between PIO (byte mode) and DMA (block mode) operation.
1: Set PIO (byte mode) operation 0: Set DMA (block mode) operation Full Duplex (Bit 12)
The Transmit Empty bit is a read only bit that indicates if the transmit FIFO is empty.
1: Transmit FIFO is empty 0: Transmit FIFO is not empty Receive Full (Bit 6)
The Full Duplex bit selects between full duplex and half duplex operation.
1: Enable full duplex. Full duplex is not allowed and does not set if the 3Wire Enable bit of the SPI Configuration register is set to `1' 0: Enable half duplex operation SS Manual (Bit 11)
The Receive Full bit is a read only bit that indicates if the receive FIFO is full.
1: Receive FIFO is full 0: Receive FIFO is not full Transmit Bit Length (Bits [5:3])
The SS Manual bit activates or deactivates SS if the SS Delay Select field of the SPI Control register is all zeros and is configured as master interface. This field only applies to master mode.
1: Activate SS, master drives SS line asserted LOW 0: Deactivate SS, master drives SS line deasserted HIGH
The Transmit Bit Length field controls whether a full byte or partial byte is to be transmitted. If Transmit Bit Length is `000' then a full byte is transmitted. If Transmit Bit Length is `001' to `111', then the value indicates the number of bits that are be transmitted.
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Receive Bit Length (Bits [2:0])
The Receive Bit Length field controls whether a full byte or partial byte is received. If Receive Bit Length is `000' then a full byte is received. If Receive Bit Length is `001' to `111', then the value indicates the number of bits that are received.
SPI Interrupt Enable Register [0xC0CC] [R/W] Figure 73. SPI Interrupt Enable Register
Bit # Field Read/Write Default Bit # 0 7 0 6 0 5 ...Reserved Field Read/Write Default 0 0 0 0 0 0 4 15 14 13 12 Reserved... 0 3 0 2 Receive Interrupt Enable R/W 0 0 1 Transmit Interrupt Enable R/W 0 0 0 Transfer Interrupt Enable R/W 0 11 10 9 8
Register Description
1: Enables byte mode transmit interrupt 0: Disables byte mode transmit interrupt Transfer Interrupt Enable (Bit 0)
The SPI Interrupt Enable register controls the SPI port.
Receive Interrupt Enable (Bit 2)
The Receive Interrupt Enable bit enables or disables the byte mode receive interrupt (RxIntVal).
1: Enable byte mode receive interrupt 0: Disable byte mode receive interrupt Transmit Interrupt Enable (Bit 1)
The Transfer Interrupt Enable bit enables or disables the block mode interrupt (XfrBlkIntVal).
1: Enables block mode interrupt 0: Disables block mode interrupt Reserved
The Transmit Interrupt Enable bit enables or disables the byte mode transmit interrupt (TxIntVal).
SPI Status Register [0xC0CE] [R]
Write all reserved bits with '0'.
Figure 74. SPI Status Register
Bit # Field Read/Write Default Bit # 0 7 FIFO Error Flag Field Read/Write Default R 0 0 0 0 0 0 6 0 5 Reserved 0 4 15 14 13 12 Reserved 0 3 0 2 Receive Interrupt Flag R 0 0 1 Transmit Interrupt Flag R 0 0 0 Transfer Interrupt Flag R 0 11 10 9 8
Register Description
The SPI Status register is a read only register that provides status for the SPI port.
FIFO Error Flag (Bit 7)
The FIFO Error Flag bit is a read only bit that indicates if a FIFO error occurred. When this bit is set to `1' and the Transmit
Empty bit of the SPI Control register is set to `1', then a Tx FIFO underflow occurred. Similarly, when set with the Receive Full bit of the SPI Control register, an Rx FIFO overflow occured.This bit automatically clears when the SPI FIFO Init Enable bit of the SPI Control register is set. 1: Indicates FIFO error 0: Indicates no FIFO error
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Receive Interrupt Flag (Bit 2)
1: Indicates a byte mode transmit interrupt triggered 0: Indicates a byte mode transmit interrupt did not trigger Transfer Interrupt Flag (Bit 0)
The Receive Interrupt Flag is a read only bit that indicates if a byte mode receive interrupt triggered.
1: Indicates a byte mode receive interrupt triggered 0: Indicates a byte mode receive interrupt did not trigger Transmit Interrupt Flag (Bit 1)
The Transfer Interrupt Flag is a read only bit that indicates a block mode interrupt triggered.
1: Indicates a block mode interrupt triggered 0: Indicates a block mode interrupt did not trigger
The Transmit Interrupt Flag is a read only bit that indicates a byte mode transmit interrupt triggered.
SPI Interrupt Clear Register [0xC0D0] [W]
Figure 75. SPI Interrupt Clear Register
Bit # Field Read/Write Default Bit # 0 7 0 6 0 5 Reserved Field Read/Write Default 0 0 0 0 0 0 0 4 15 14 13 12 Reserved 0 3 0 2 0 1 Transmit Interrupt Clear W 0 0 0 Transfer Interrupt Clear W 0 11 10 9 8
Register Description
Transfer Interrupt Clear (Bit 0)
The SPI Interrupt Clear register is a write only register that allows the SPI Transmit and SPI Transfer Interrupts to be cleared.
Transmit Interrupt Clear (Bit 1)
The Transfer Interrupt Clear bit is a write only bit that clears the block mode interrupt. This bit is self clearing.
1: Clear the block mode interrupt 0: No function Reserved
The Transmit Interrupt Clear bit is a write only bit that clears the byte mode transmit interrupt. This bit is self clearing.
1: Clear the byte mode transmit interrupt 0: No function SPI CRC Control Register [0xC0D2] [R/W]
Write all reserved bits with '0'.
Figure 76. SPI CRC Control Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 0 0 R/W 0 7 R/W 0 6 15 CRC Mode 14 13 CRC Enable R/W 0 5 12 CRC Clear R/W 0 4 ...Reserved 0 0 0 0 11 Receive CRC R/W 0 3 10 One in CRC R 0 2 9 Zero in CRC R 0 1 8 Reserved... 0 0
Register Description
CRC Mode (Bits [15:14)
The SPI CRC Control register provides control over the CRC source and polynomial value.
The CRCMode field selects the CRC polynomial as defined in Table 46 on page 70.
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Table 46. CRC Mode Definition CRCMode [15:14] CRC Polynomial
Receive CRC (Bit 11)
The Receive CRC bit determines whether the receive bit stream or the transmit bit stream is used for the CRC data input in full duplex mode. This bit is a don't care in half duplex mode.
1: Assigns the receive bit stream 0: Assigns the transmit bit stream One in CRC (Bit 10)
00 01 10 11
MMC 16 bit: X^16 + X^12 + X^5 + 1(CCITT Standard) CRC7 7 bit: X^7+ X^3 + 1 MST 16 bit: X^16+ X^15 + X^2 + 1 Reserved, 16 bit polynomial 1
The One in CRC bit is a read only bit that indicates if the CRC value is all zeros or not
1: CRC value is not all zeros 0: CRC value is all zeros Zero in CRC (Bit 9)
CRC Enable (Bit 13)
The CRC Enable bit enables or disables the CRC operation.
1: Enables CRC operation 0: Disables CRC operation CRC Clear (Bit 12)
The Zero in CRC bit is a read only bit that indicates if the CRC value is all ones or not.
1: CRC value is not all ones 0: CRC value is all ones Reserved
The CRC Clear bit clears the CRC with a load of all ones. This bit is self clearing and always reads `0'.
1: Clear CRC with all ones 0: No Function
Write all reserved bits with '0'.
SPI CRC Value Register [0xC0D4] [R/W] Figure 77. SPI CRC Value Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 ...CRC R/W 1 R/W 1 R/W 1 R/W 1 15 14 13 12 CRC... R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 11 10 9 8
Register Description
CRC (Bits [15:0])
The SPI CRC Value register contains the CRC value.
The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value is a seven bit value [6:0]. Therefore, bits [15:7] are invalid in CRC7 mode.
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SPI Data Register [0xC0D6] [R/W] Figure 78. SPI Data Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W X R/W X R/W X R/W X X 7 X 6 X 5 X 4 Data R/W X R/W X R/W X R/W X 15 14 13 12 Reserved X 3 X 2 X 1 X 0 11 10 9 8
Register Description
Data (Bits [7:0])
The SPI Data register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO byte mode. This receive data is valid when the Receive Interrupt Bit of the SPI Status register is set to `1' (RxIntVal triggers) or the Receive Data Ready bit of the SPI Control register is set to `1'. Writing to this register in PIO byte mode initiates a transfer of data, the number of bits defined by Transmit Bit Length field in the SPI Control register.
SPI Transmit Address Register [0xC0D8] [R/W]
The Data field contains data received or to be transmitted on the SPI port.
Reserved
Write all reserved bits with '0'.
Figure 79. SPI Transmit Address Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8
Register Description
Address (Bits [15:0])
The SPI Transmit Address register is used as the base address for the SPI transmit DMA.
The Address field sets the base address for the SPI transmit DMA.
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SPI Transmit Count Register [0xC0DA] [R/W] Figure 80. SPI Transmit Count Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 15 14 13 Reserved 0 5 0 4 ...Count R/W 0 R/W 0 R/W 0 R/W 0 0 3 R/W 0 2 12 11 10 9 Count... R/W 0 1 R/W 0 0 8
Register Description
Reserved
The SPI Transmit Count register designates the block byte length for the SPI transmit DMA transfer.
Count (Bits [10:0])
Write all reserved bits with '0'.
The Count field sets the count for the SPI transmit DMA transfer.
SPI Receive Address Register [0xC0DC [R/W] Figure 81. SPI Receive Address Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Address... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8
Register Description
Address (Bits [15:0])
The SPI Receive Address register is issued as the base address for the SPI Receive DMA.
The Address field sets the base address for the SPI receive DMA.
SPI Receive Count Register [0xC0DE] [R/W] Figure 82. SPI Receive Count Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 15 14 13 Reserved 0 5 0 4 ...Count R/W 0 R/W 0 R/W 0 R/W 0 0 3 R/W 0 2 12 11 10 9 Count... R/W 0 1 R/W 0 0 8
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Register Description
UART Registers
The SPI Receive Count register designates the block byte length for the SPI receive DMA transfer.
Count (Bits [10:0])
There are three registers dedicated to UART operation. Each of these registers is covered in this section and summarized in Table 47.
Table 47. UART Registers Register Name UART Control Register UART Status Register UART Data Register Address 0xC0E0 R/W R/W R R/W
The Count field sets the count for the SPI receive DMA transfer.
Reserved
Write all reserved bits with '0'.
0xC0E2 0xC0E4
UART Control Register [0xC0E0] [R/W] Figure 83. UART Control Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 7 0 6 ...Reserved 0 0 0 5 0 4 Scale Select R/W 0 R/W 0 15 14 13 12 Reserved... 0 3 0 2 Baud Select R/W 1 R/W 1 0 1 0 0 UART Enable R/W 1 11 10 9 8
Register Description
Table 48. UART Baud Select Definition Baud Select Baud Rate w/ DIV8 = 0 Baud Rate w/ DIV8 = 1 [3:1]
The UART Control register enables or disables the UART, allowing GPIO28 (UART_TXD) and GPIO27 (UART_RXD) to be freed up for general use. This register must also be written to set the baud rate, which is based on a 48 MHz clock.
Scale Select (Bit 4)
000 001 010 011 100 101 110 111
115.2 KBaud 57.6 KBaud 38.4 KBaud 28.8 KBaud 19.2 KBaud 14.4 KBaud 9.6 KBaud 7.2 KBaud
14.4 KBaud 7.2 KBaud 4.8 KBaud 3.6 KBaud 2.4 KBaud 1.8 KBaud 1.2 KBaud 0.9 KBaud
The Scale Select bit acts as a prescaler that divide the baud rate by eight.
1: Enable prescaler 0: Disable prescaler Baud Select (Bits [3:1])
Refer to Table 48 for a definition of this field.
UART Enable (Bit 0)
The UART Enable bit enables or disables the UART.
1: Enable UART 0: Disable UART. This allows GPIO28 and GPIO27 to be used for general use. Reserved
Write all reserved bits with '0'.
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UART Status Register [0xC0E2] [R] Figure 84. UART Status Register
Bit # Field Read/Write Default Bit # Field Read/Write Default 0 0 0 0 7 0 6 0 5 ...Reserved 0 0 0 4 0 3 15 14 13 12 Reserved... 0 2 0 1 Receive Full R 0 0 0 Transmit Full R 0 0 11 10 9 8
Register Description
Transmit Full (Bit 0)
The UART Status register is a read only register that indicates the status of the UART buffer.
Receive Full (Bit 1)
The Receive Full bit indicates whether the receive buffer is full. It can be programmed to interrupt the CPU as interrupt #5 when the buffer is full. This can be done though the UART bit of the Interrupt Enable register (0xC00E). This bit is automatically cleared when data is read from the UART Data register.
1: Receive buffer full 0: Receive buffer empty UART Data Register [0xC0E4] [R/W]
The Transmit Full bit indicates whether the transmit buffer is full. It can be programmed to interrupt the CPU as interrupt #4 when the buffer is empty. This can be done though the UART bit of the Interrupt Enable register (0xC00E). This bit is automatically set to `1' after data is written by EZ-Host to the UART Data register (to be transmitted). This bit is automatically cleared to `0' after the data is transmitted.
1: Transmit buffer full (transmit busy) 0: Transmit buffer is empty and ready for a new byte of data
Figure 85. UART Data Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 0 5 0 4 Data R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Reserved 0 3 0 2 0 1 0 0 11 10 9 8
Register Description
Data (Bits [7:0])
The UART Data register contains data to be transmitted or received from the UART port. Data written to this register starts a data transmission and also causes the UART Transmit Full Flag of the UART Status register to set. When data received on the UART port is read from this register, the UART Receive Full Flag of the UART Status register is cleared.
The Data field is where the UART data to be transmitted or received is located.
Reserved
Write all reserved bits with '0'.
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PWM Registers
There are eleven registers dedicated to PWM operation. Each of these registers are covered in this section and summarized in Table 49.
Table 49. PWM Registers Register Name Address R/W
PWM Control Register PWM Maximum Count Register PWM0 Start Register PWM0 Stop Register PWM1 Start Register PWM1 Stop Register PWM2 Start Register PWM2 Stop Register PWM3 Start Register PWM3 Stop Register PWM Cycle Count Register
PWM Control Register [0xC0E6] [R/W] Figure 86. PWM Control Register
Bit # Field Read/Write Default Bit # 15 PWM Enable R/W 0 7 PWM 3 Polarity Select R/W 0 0 6 PWM 2 Polarity Select R/W 0 14 13 Reserved 0 5 PWM 1 Polarity Select R/W 0 0 4 PWM 0 Polarity Select R/W 0 R/W 0 3 PWM 3 Enable R/W 0 12 11
0xC0E6 0xC0E8 0xC0EA 0xC0EC 0xC0EE 0xC0F0 0xC0F2 0xC0F4 0xC0F6 0xC0F8 0xC0FA
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
10 Prescale Select R/W 0 2 PWM 2 Enable R/W 0
9
8 Mode Select
R/W 0 1 PWM 1 Enable R/W 0
R/W 0 0 PWM 0 Enable R/W 0
Field Read/Write Default
Register Description
Table 50. Prescaler Select Definition Prescale Select [11:9] Frequency
The PWM Control register provides high level control over all four of the PWM channels.
PWM Enable (Bit 15)
000 001 010 011 100 101 110 111
48.00 MHz 24.00 MHz 06.00 MHz 01.50 MHz 375 kHz 93.80 kHz 23.40 kHz 05.90 kHz
The PWM Enable bit starts and stops PWM operation.
1: Start operation 0: Stop operation Prescale Select (Bits [11:9])
The Prescale Select field sets the frequency of all the PWM channels as defined in Table 50.
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Mode Select (Bit 8)
PWM 0 Polarity Select (Bit 4)
The Mode Select bit selects between continuous PWM cycling and one shot mode. The default is continuous repeat.
1: Enable One Shot mode. The mode runs the number of counter cycles set in the PWM Cycle Count register and then stops. 0: Enable Continuous mode. Runs in continuous mode and starts over after the PWM cycle count is reached. PWM 3 Polarity Select (Bit 7)
The PWM 0 Polarity Select bit selects the polarity for PWM 0.
1: Sets the polarity to active HIGH or rising edge pulse 0: Sets the polarity to active LOW PWM 3 Enable (Bit 3)
The PWM 3 Enable bit enables or disables PWM 3.
1: Enable PWM 3 0: Disable PWM 3 PWM 2 Enable (Bit 2)
The PWM 3 Polarity Select bit selects the polarity for PWM 3.
1: Sets the polarity to active HIGH or rising edge pulse 0: Sets the polarity to active LOW PWM 2 Polarity Select (Bit 6)
The PWM 2 Enable bit enables or disables PWM 2.
1: Enable PWM 2 0: Disable PWM 2 PWM 1 Enable (Bit 1)
The PWM 2 Polarity Select bit selects the polarity for PWM 2.
1: Sets the polarity to active HIGH or rising edge pulse 0: Sets the polarity to active LOW PWM 1 Polarity Select (Bit 5)
The PWM 1 Enable bit enables or disables PWM 1.
1: Enable PWM 1 0: Disable PWM 1 PWM 0 Enable (Bit 0)
The PWM 1 Polarity Select bit selects the polarity for PWM 1.
1: Sets the polarity to active HIGH or rising edge pulse 0: Sets the polarity to active LOW
The PWM 0 Enable bit enables or disables PWM 0.
1: Enable PWM 0 0: Disable PWM 0
PWM Maximum Count Register [0xC0E8] [R/W] Figure 87. PWM Maximum Count Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 0 5 15 14 13 Reserved 0 4 ...Count R/W 0 R/W 0 R/W 0 R/W 0 0 3 0 2 R/W 0 1 12 11 10 9 Count... R/W 0 0 8
Register Description
Count (Bits [9:0])
The PWM Maximum Count register designates the maximum window for each pulse cycle. Each count tick is based on the clock frequency set in the PWM Control register.
The Count field sets the maximum cycle time.
Reserved
Write all reserved bits with '0'.
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PWM n Start Register [R/W] * PWM 0 Start Register 0xC0EA * PWM 1 Start Register 0xC0EE * PWM 2 Start Register 0xC0F2 * PWM 3 Start Register 0xC0F6 Figure 88. PWM n Start Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 7 0 6 0 5 15 14 13 Reserved 0 4 ...Address R/W 0 R/W 0 R/W 0 R/W 0 0 3 0 2 R/W 0 1 12 11 10 9 Address... R/W 0 0 8
Register Description
Address (Bits [9:0])
The PWM n Start register designates where in the window defined by the PWM Maximum Count register to start the PWM pulse for a supplied channel.
The Address field designates when to start the PWM pulse. If this start value is equal to the Stop Count Value then the output stays at false.
Reserved
Write all reserved bits with '0'.
PWM n Stop Register [R/W] * PWM 0 Stop Register 0xC0EC * PWM 1 Stop Register 0xC0F0 * PWM 2 Stop Register 0xC0F4 * PWM 3 Stop Register 0xC0F8 Figure 89. PWM n Stop Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 0 0 0 15 14 13 Reserved 0 0 0 R/W 0 12 11 10 9 Address... R/W 0 8
7
6
5
4
3
...Address R/W 0
2
R/W 0
1
R/W 0
0
R/W 0
Register Description
The PWM n Stop register designates where in the window defined by the PWM Maximum Count register to stop the PWM pulse for a supplied channel.
Address (Bits [9:0])
output stays at `0'. If the PWM Stop value is greater then the PWM Maximum Count value then the output stays at true.
Reserved
Write all reserved bits with '0'.
The Address field designates when to stop the PWM pulse. If the PWM Start value is equal to the PWM Stop value then the
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PWM Cycle Count Register [0xC0FA] [R/W] Figure 90. PWM Cycle Count Register
Bit # Field Read/Write Default Bit # Field Read/Write Default R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 ...Count R/W 0 R/W 0 R/W 0 R/W 0 15 14 13 12 Count... R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 11 10 9 8
Register Description
Count (Bits [9:0])
The PWM Cycle Count register designates the number of cycles to run when in one shot mode. One shot mode is enabled by setting the Mode Select bit of the PWM Control register to `1'.
The Count field designates the number of cycles (plus one) to run when in one shot mode. For example, Cycles = PWM Cycle Count + 1, therefore for two cycles set PWM Cycle Count = 1.
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Pin Diagram
Figure 91. EZ-Host Pin Diagram
GPIO0/D0 GPIO2/D2 GPIO6/D6 GPIO7/D7 GPIO1/D1 GPIO3/D3 GPIO4/D4 GPIO5/D5 Reserved
nBEL/A0
nRESET
nBEH
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A1 A2 A3 DM2B DP2B AGND A4 A5 DM2A DP2A OTGVBUS CSWITCHB CSWITCHA VSWITCH BOOSTGND BOOSTVCC A6 DM1B DP1B A7 AVCC DM1A DP1A A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND A10 XTALOUT XTALIN A11 A12 75 74 73 72 71 70 69 68 67 66 65 GND D8/MISO D9/nSSI D10/SCK D11/MOSI D12/TXD D13/RXD D14/RTS D15/CTS GPIO8/D8/MISO GPIO9/D9/nSSI nWR VCC nRD GPIO10/D10/SCK GPIO11/D11/MOSI GPIO12/D12 GPIO13/D13 GPIO14/D14 GPIO15/D15/nSSI GPIO16/A0/TXD/PWM0 GPIO17/A1/RXD/PWM1 GPIO18/A2/RTS/PWM2 GPIO19/A0/CS0 GND
GND
VCC
A16
A17
A18
D7
D0
D3
D1
D2
D4
D6
D5
CY7C67300
64 63 62 61 60 59 58 57 56 55 54 53 52 51
A13
A14
nXMEMSEL
nXROMSEL
GPIO30/SDA
GPIO29/OTGID
GPIO28/TX
GPIO27/RX
nXRAMSEL
VCC
GPIO26/CTS/PWM3
GPIO25/IRQ1
A15/CLKSEL
GPIO31/SCL
GPIO24/INT/IORDY/IRQ0
GPIO23/nRD/IOR
GPIO22/nWR/IOW
GPIO21/nCS
GPIO20/A1/CS1
Pin Descriptions
Table 51. Pin Descriptions Pin 67 Name D15/CTS Type IO Description D15: External Memory Data Bus CTS: HSS CTS D14: External Memory Data Bus RTS: HSS RTS D13: External Memory Data Bus RXD: HSS RXD (Data is received on this pin) D12: External Memory Data Bus TXD: HSS TXD (Data is transmitted from this pin)
68 69 70
D14/RTS D13/RXD D12/TXD
IO IO IO
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Table 51. Pin Descriptions (continued) Pin 71 Name D11/MOSI Type IO Description D11: External Memory Data Bus MOSI: SPI MOSI D10: External Memory Data Bus SCK: SPI SCK D9: External Memory Data Bus nSSI: SPI nSSI D8: External Memory Data Bus MISO: SPI MISO External Memory Data Bus
72 73 74 76 77 78 79 80 81 82 83 33 32 31 30 27 25 24 20 17 8 7 3 2 1 99 98 64 62 97 95 96 34 35 36 38
D10/SCK D9/nSSI D8/MISO D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 nBEL/A0 nBEH nWR nRD A16 A17 A18 nXMEMSEL nXROMSEL nXRAMSEL A15/CLKSEL
IO IO IO IO IO IO IO IO IO IO IO Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output IO
External Memory Address Bus
39 40
GPIO31/SCK GPIO30/SDA
IO IO
nBEL: Low Byte Enable for 16-bit memories A0: External Memory Address bit A0 for 0-8 bit memories High Byte Enable for 16-bit memories External Memory Write pulse External Memory Read pulse A16: External SRAM A16 A17: External SRAM A17 A18: External SRAM A18 External Memory Select 0 External Memory Select 1 External Memory Select 2 A15: External SRAM A15 CLKSEL: Sampled directly after reset to determine what crystal or clock source frequency is being used. 12 MHz is required for normal operation so the CLKSEL pin must have a 47K ohm pull up to VCC. After reset this pin functions as A15. GPIO31: General Purpose IO SCK: I2C EEPROM SCK GPIO30: General Purpose IO SDA: I2C EEPROM SDA
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Table 51. Pin Descriptions (continued) Pin 41 Name GPIO29/OTGID Type IO Description GPIO29: General Purpose IO OTGID: Input for OTG ID pin. When used as OTGID, tie this pin high through an external pull up resistor. Assuming VCC = 3.0V, a 10K to 40K resistor must be used. GPIO28: General Purpose IO TX: UART TX (Data is transmitted from this pin) GPIO27: General Purpose IO RX: UART RX (Data is received on this pin) GPIO26: General Purpose IO CTS: HSS CTS PWM3: PWM channel 3 GPIO25: General Purpose IO IRQ1: Interrupt Request 1. See Register 0xC006. This pin is also one of two possible GPIO wakeup sources. GPIO24: General Purpose IO INT: HPI INT IORDY: IDE IORDY IRQ0: Interrupt Request 0. See Register 0xC006. This pin is also one of two possible GPIO wakeup sources. GPIO23: General Purpose IO nRD: HPI nRD IOR: IDE IOR GPIO22: General Purpose IO nWR: HPI nWR IOW: IDE IOW GPIO21: General Purpose IO nCS: HPI nCS GPIO20: General Purpose IO A1: HPI A1 CS1: IDE CS1 GPIO19: General Purpose IO A0: HPI A0 CS0: IDE CS0 GPIO18: General Purpose IO A2: IDE A2 RTS: HSS RTS PWM2: PWM channel 2 GPIO17: General Purpose IO A1: IDE A1 RXD: HSS RXD (Data is received on this pin) PWM1: PWM channel 1 GPIO16: General Purpose IO A0: IDE A0 TXD: HSS TXD (Data is transmitted from this pin) PWM0: PWM channel 0 GPIO15: General Purpose IO D15: D15 for HPI or IDE nSSI: SPI nSSI GPIO14: General Purpose IO D14: D14 for HPI or IDE GPIO13: General Purpose IO D13: D13 for HPI or IDE GPIO12: General Purpose IO D12: D12 for HPI or IDE
42 43 44
GPIO28/TX GPIO27/RX GPIO26/CTS/PWM3
IO IO IO
45
GPIO25/IRQ1
IO
46
GPIO24/INT/ IORDY/IRQ0
IO
47
GPIO23/nRD/IOR
IO
48
GPIO22/nWR/IOW
IO
49 50
GPIO21/nCS GPIO20/A1/CS1
IO IO
52
GPIO19/A0/CS0
IO
53
GPIO18/A2/RTS/ PWM2
IO
54
GPIO17/A1/RXD/ PWM1
IO
55
GPIO16/A0/TXD/ PWM0
IO
56
GPIO15/D15/nSSI
IO
57 58 59
GPIO14/D14 GPIO13/D13 GPIO12/D12
IO IO IO
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Table 51. Pin Descriptions (continued) Pin 60 Name GPIO11/D11/MOSI Type IO Description GPIO11: General Purpose IO D11: D11 for HPI or IDE MOSI: SPI MOSI GPIO10: General Purpose IO D10: D10 for HPI or IDE SCK: SPI SCK GPIO9: General Purpose IO D9: D9 for HPI or IDE nSSI: SPI nSSI GPIO8: General Purpose IO D8: D8 for HPI or IDE MISO: SPI MISO GPIO7: General Purpose IO D7: D7 for HPI or IDE GPIO6: General Purpose IO D6: D6 for HPI or IDE GPIO5: General Purpose IO D5: D5 for HPI or IDE GPIO4: General Purpose IO D4: D4 for HPI or IDE GPIO3: General Purpose IO D3: D3 for HPI or IDE GPIO2: General Purpose IO D2: D2 for HPI or IDE GPIO1: General Purpose IO D1: D1 for HPI or IDE GPIO0: General Purpose IO D0: D0 for HPI or IDE USB Port 1A D- USB Port 1A D+ USB Port 1B D- USB Port 1B D+ USB Port 2A D- USB Port 2A D+ USB Port 2B D- USB Port 2B D+ Crystal input or Direct Clock input Crystal output. Leave floating if direct clock source is used. Reset Tie to Gnd for normal operation. Booster Power input: 2.7V to 3.6V Booster switching output
61
GPIO10/D10/SCK
IO
65
GPIO9/D9/nSSI
IO
66
GPIO8/D8/MISO
IO
86 87 89 90 91 92 93 94 22 23 18 19 9 10 4 5 29 28 85 84 16 14 15 11 13 12 21 6 37, 63, 88 26, 51, 75, 100
GPIO7/D7 GPIO6/D6 GPIO5/D5 GPIO4/D4 GPIO3/D3 GPIO2/D2 GPIO1/D1 GPIO0/D0 DM1A DP1A DM1B DP1B DM2A DP2A DM2B DP2B XTALIN XTALOUT nRESET Reserved BOOSTVCC VSWITCH BOOSTGND OTGVBUS CSWITCHA CSWITCHB AVCC AGND VCC GND
IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Input Output Input Power Analog Output Ground Analog IO Analog Analog Power Ground Power Ground
Booster Ground USB OTG Vbus Charge Pump Capacitor Charge Pump Capacitor USB Power USB Ground Main VCC Main Ground
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Absolute Maximum Ratings
This section lists the absolute maximum ratings. Stresses above those listed can cause permanent damage to the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability. Storage Temperature ............................................................................................................................................-40C to +125C Ambient Temperature with Power Supplied ............................................................................................................-40C to +85C Supply Voltage to Ground Potential ...........................................................................................................................0.0V to +3.6V DC Input Voltage to Any General Purpose Input Pin .............................................................................................................. 5.5V DC Voltage Applied to XTALIN....................................................................................................................... -0.5V to VCC + 0.5V Static Discharge Voltage ................................................................................................................................................... > 2000V Max Output Current, per IO ................................................................................................................................................... 4 mA
Operating Conditions
TA (Ambient Temperature Under Bias)....................................................................................................................-40C to +85C Supply Voltage (VCC, AVCC) ....................................................................................................................................+3.0V to +3.6V Supply Voltage (BoostVCC)[7] ...................................................................................................................................+2.7V to +3.6V Ground Voltage ........................................................................................................................................................................... 0V FOSC (Oscillator or Crystal Frequency) ............................................................................................................. 12 MHz 500 ppm ............................................................................................................................................................................ Parallel Resonant
Crystal Requirements (XTALIN, XTALOUT)
Table 52. Crystal Requirements Crystal Requirements (XTALIN, XTALOUT) Min. Typical Max. Unit
Parallel Resonant Frequency Frequency Stability Load Capacitance Driver Level Startup Time Mode of Vibration: Fundamental -500 20
12 +500 33 500 5
MHz PPM pF W ms
DC Characteristics
Table 53. DC Characteristics [8] Parameter Description Conditions Min. Typ. Max. Unit
VCC, AVCC BoosVCC VIH VIL II VOH VOL IOH IOL
Supply Voltage Supply Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Voltage HIGH Output LOW Voltage Output Current HIGH Output Current LOW 0< VIN < VCC IOUT = 4 mA IOUT = -4 mA
3.0 2.7 2.0 -10.0 2.4
3.3
3.6 3.6 5.5 0.8 +10.0 0.4
V V V V
A
V V mA mA 10 10 20 20
Notes 7. The on-chip voltage booster circuit boosts BoostVCC to provide a nominal 3.3V VCC supply. 8. All tests were conducted with Charge pump off.
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Table 53. DC Characteristics (continued)[8] Parameter Description Conditions Min. Typ. Max. Unit
CIN VHYS ICC[9, 10] ICCB
[9, 10]
Input Pin Capacitance Hysteresis on nReset Pin Supply Current Supply Current with Booster Enabled Sleep Current
Except D+/D- D+/D- 250 4 transceivers powered 4 transceivers powered USB Peripheral: includes 1.5K internal pull up Without 1.5K internal pull up 80 135 210 5 190 5
10 15 100 180 500 30 500 30
pF pF mV mA mA
A A A A
ISLEEP
ISLEEPB
Sleep Current with Booster Enabled USB Peripheral: includes 1.5K internal pull up Without 1.5K internal pull up
Table 54. DC Characteristics: Charge Pump Parameter Description Conditions Min. Typ. Max. Unit
VA_VBUS_OUT TA_VBUS_RISE IA_VBUS_OUT CDRD_VBUS VA_VBUS_LKG VDRD_DATA_LKG ICHARGE ICHARGEB IB_DSCHG_IN VA_VBUS_VALID VA_SESS_VALID VB_SESS_VALID VA_SESS_END E RPD RA_BUS_IN RB_SRP_UP RB_SRP_DWN
USB Transceiver
Regulated OTGVBUS Voltage VBUS Rise Time Maximum Load Current OUTVBUS Bypass Capacitance OTGVBUS Leakage Voltage Dataline Leakage Voltage Charge Pump Current Draw
8 mA< ILOAD < 10 mA ILOAD = 10 mA
4.4 8
5.25 100 10 6.5 200 342 20 0 30 0 20 1 45 5 8
V ms mA pF mV mV mA mA mA mA mA V
4.4V< VBUS < 5.25V OTGVBUS not driven ILOAD = 8 mA ILOAD = 0 mA
1.0
Charge Pump Current Draw with ILOAD = 8 mA Booster Active ILOAD = 0 mA B-Device (SRP Capable) Discharge Current A-Device VBUS Valid A-Device Session Valid B-Device Session Valid B-Device Session End Efficiency When Loaded Data Line Pull Down A-device VBUS Input Impedance to GND B-device VBUS SRP Pull Up B-device VBUS SRP Pull Down VBUS is not being driven Pull up voltage = 3.0V ILOAD = 8 mA, VCC = 3.3V 14.25 40 281 656 0V< VBUS < 5.25V 4.4 0.8 0.8 0.2
2.0 4.0 0.8 75 24.8 100
V V V %
k

USB 2.0 certified in full- and low-speed modes.
Notes 9. ICC and ICCB values are the same regardless of USB host or peripheral configuration. 10. There is no appreciable difference in ICC and ICCB values when only two transceivers are powered.
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AC Timing Characteristics
Reset Timing
tRESET
nRESET
tIOACT
nRD or nWRL or nWRH
Reset Timing
Table 55. Reset Timing Parameters Parameter Description Min. Typical Max. Unit
tRESET tIOACT
nRESET Pulse Width nRESET HIGH to nRD or nWRx active
16 200
clocks[11] s
Clock Timing
tCLK
XTALIN
tHIGH
tLOW tFALL tRISE
Clock Timing
Table 56. Clock Timing Parameters Parameter Description Min. Typical Max. Unit
fCLK vXINH[12] tCLK tHIGH tLOW tRISE tFALL Duty Cycle
Clock Frequency Clock Input High (XTALOUT left floating) Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time 45 1.5 83.17 36 36
12.0 3.0 83.33 3.6 83.5 44 44 5.0 5.0 55
MHz V ns ns ns ns ns %
Notes 11. Clock is 12 MHz nominal. 12. vXINH is required to be 3.0 V to obtain an internal 50/50 duty cycle clock.
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SRAM Read Cycle[15]
Address
CS
t AR tCR
RD
t RPW t CDH t AC t RDH
Din
Data Valid
Table 57. SRAM Read Cycle Parameters Parameter Description Min. Typical Max. Unit
tCR tRDH tCDH tRPW[13] tAR tAC[14]
CS LOW to RD LOW RD HIGH to Data Hold CS HIGH to Data Hold RD LOW Time RD LOW to Address Valid RAM Access to Data Valid
1 0 0 38 45 0 12
ns ns ns ns ns ns
Notes 13. 0 wait state cycle. 14. tAC External SRAM access time = 12 ns for zero and one wait states. The External SRAM access time = 12 ns + (n - 1)*T for wait states = n, n > 1, T = 48 MHz clock period. 15. Read timing is applicable for nXMEMSEL, nXRAMSEL, and nXROMSEL.
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SRAM Write Cycle [17]
Address
t AW tCSW
CS
tWC t WPW
WE
t DW
t DH
Dout
Data Valid
Table 58. SRAM Write Cycle Parameters Parameter Description Min. Typical Max. Unit
tAW tCSW tDW tWPW[16] tDH tWC
Write Address Valid to WE LOW CS LOW to WE LOW Data Valid to WE HIGH WE Pulse Width Data Hold from WE HIGH WE HIGH to CS HIGH
7 7 15 15 4.5 13
ns ns ns ns ns ns
Notes 16. tWPW The write pulse width = 18.8 ns min. for zero and one wait states. The write pulse = 18.8 ns + (n - 1)*T for wait states = n, n > 1, T = 48 MHz clock period. 17. Write timing is applicable for nXMEMSEL, nXRAMSEL and nXROMSEL.
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I2C EEPROM Timing-Serial IO
tLOW tHIGH
tR
tF
SCL
tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO tBUF
SDA IN
tAA tDH
SDA OUT
Table 59. I2C EEPROM Timing Parameters Parameter Description Min. Typical Max. Unit
fSCL tLOW tHIGH tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH
Clock Frequency Clock Pulse Width Low Clock Pulse Width High Clock Low to Data Out Valid Bus Idle Before New Transmission Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Input Rise Time Input Fall Time Stop Setup Time Data Out Hold Time 600 0 1300 600 900 1300 600 600 0 100
400
kHz ns ns ns ns ns ns ns ns
300 300
ns ns ns ns
Document #: 38-08015 Rev. *H
Page 88 of 98
CY7C67300
HPI (Host Port Interface) Write Cycle Timing
tCYC
tASU
tWP
tAH
ADDR [1:0]
tCSSU tCSH
nCS
nWR
nRD
Dout [15:0]
tDSU tWDH
Table 60. HPI Write Cycle Timing Parameters Parameter Description Min. Typical Max. Unit
tASU tAH tCSSU tCSH tDSU tWDH tWP tCYC
Address Setup Address Hold Chip Select Setup Chip Select Hold Data Setup Write Data Hold Write Pulse Width Write Cycle Time
-1 -1 -1 -1 6 2 2 6
ns ns ns ns ns ns T[18] T[18]
Notes 18. T = system clock period = 1/48 MHz.
Document #: 38-08015 Rev. *H
Page 89 of 98
CY7C67300
HPI (Host Port Interface) Read Cycle Timing
tCYC
tASU
tRP
tAH
ADDR [1:0]
tCSSU tCSH
nCS
nWR
tRDH
nRD
Din [15:0]
tACC tRDH
Table 61. HPI Read Cycle Timing Parameters Parameter Description Min. Typical Max. Unit
tASU tAH tCSSU tCSH tACC tRDH tRP tCYC
Address Setup Address Hold Chip Select Setup Chip Select Hold Data Access Time, from HPI_nRD falling Read Data Hold, relative to the earlier of HPI_nRD rising or HPI_nCS rising Read Pulse Width Read Cycle Time
-1 -1 -1 -1 1 1.5 2 6 7
ns ns ns ns T[18] ns T[18] T[18]
Document #: 38-08015 Rev. *H
Page 90 of 98
CY7C67300
IDE Timing
The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment-4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18.
HSS BYTE Mode Transmit
qt_clk CPU_A[2:0] CPUHSS_cs CPU_wr TxRdy flag HSS_TxD
start bit bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 stop bit start bit BT BT CPU may start another BYTE transmit right after TxRdy goes high
Byte transmit triggered by a CPU write to the HSS_TxData register
TxRdy low to start bit delay: 0 min, BT max when starting from IDEL. For back to back transmit, new START Bit begins immediately following previous STOP bit. (BT = bit period)
start of last data bit to TxRdy high: 0 min, 4 T max. (T is qt_clk period)
programmable 1 or 2 stop bits. 1 stop bit shown.
qt_clk, CPU_A, CPUHSS_cs, CPU_wr are internal signals, included in the diagram to illustrate the relationship between CPU operations and HSS port operations. Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_TxD HIGH = data bit value `1'. BT = bit time = 1/baud rate.
HSS Block Mode Transmit
BT HSS_TxD
t
GAP
BLOCK mode transmit timing is similar to BYTE mode, except the STOP bit time is controlled by the HSS_GAP value. The BLOCK mode STOP bit time, tGAP = (HSS_GAP - 9) BT, where BT is the bit time, and HSS_GAP is the content of the HSS Transmit Gap register [0xC074]. The default tGAP is 2 BT. BT = bit time = 1/baud rate.
HSS BYTE and BLOCK Mode Receive
BT +/- 5% BT +/- 5% received byte added to receive FIFO during the final data bit time
HSS_RxD
start bit
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
stop bit
start bit
10 BT +/- 5%
Receive data arrives asynchronously relative to the internal clock. Incoming data bit rate may deviate from the programmed baud rate clock by as much as 5% (with HSS_RATE value of 23 or higher). BYTE mode received bytes are buffered in a FIFO. The FIFO not empty condition becomes the RxRdy flag. BLOCK mode received bytes are written directly to the memory system. Bit 0 is LSB of data byte. Data bits are HIGH true: HSS_RxD HIGH = data bit value `1'. BT = bit time = 1/baud rate.
Document #: 38-08015 Rev. *H
Page 91 of 98
CY7C67300
Hardware CTS/RTS Handshake
tCTShold tCTSsetup HSS_RTS tCTSsetup tCTShold
HSS_CTS HSS_TxD
Start of transmission delayed until HSS_CTS goes high
Start of transmission not delayed by HSS_CTS
tCTSsetup: HSS_CTS setup time before HSS_RTS = 1.5T min. tCTShold: HSS_CTS hold time after START bit = 0 ns min. T = 1/48 MHz. When RTS/CTS hardware handshake is enabled, transmission can be help off by deasserting HSS_CTS at least 1.5T before HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit. HSS_RTS is deasserted in the third data bit time. An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit.
Register Summary
Table 62. Register Summary
R/W Address Register Bit 15 Bit 7 Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 3 Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Default High Default Low
R R
0x0140 0x0142
HPI Breakpoint Interrupt Routing
Address... ...Address VBUS to HPI ID to HPI Enable Enable Resume2 to HPI Enable Resume1 to HPI Enable SOF/EOP2 to SOF/EOP2 to SOF/EOP1 to SOF/EOP1 to Reset2 to HPI HPI Swap 1 HPI Enable CPU Enable HPI Enable CPU Enable Enable Enable Reserved Done2 to HPI Done1 to HPI Reset1 to HPI HPI Swap 0 Enable Enable Enable Enable
0000 0000 0000 0000 0001 0100 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx Stall Enable ISO Enable NAK Interrupt Direction Enable Select Enable ARM Enable xxxx xxxx xxxx xxxx xxxx xxxx Count... Overflow Flag NAK Flag Length Setup Exception Flag Flag Sequence Status Underflow Flag Timeout Flag xxxx xxxx xxxx xxxx OUT IN xxxx xxxx Exception Flag Exception Flag Error Flag ACK Flag xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 Global Interrupt Enable Negative Flag Reserved Overflow Flag Carry Flag Zero Flag 000x xxxx 0000 0001 000x xxxx xxxx xxxx xxxx xxxx UD HSS XD Enable Reserved SPI Enable SPI XD Enable SAS Enable Interrupt 1 Polarity Select CPU Speed Host/Device 2A Wake Enable Host/Device 1B Wake Enable Host/Device 1A Wake Enable OTG Wake Enable Reserved HSS Wake Enable Sleep Enable SPI Wake Enable Halt Enable Mode Select Interrupt 1 Enable Interrupt 0 Polarity Select Interrupt 0 Enable 0000 0000 0000 0000
W R/W
1: 0x0144 SIEXmsg 2: 0x0148 0x02n0 Device n Endpoint n Control
Data... ...Data Reserved IN/OUT Sequence Ignore Enable Select
R/W R.W R/W
0x02n2 0x02n4 0x02n6
Device n Endpoint n Address Device n Endpoint n Count Device n Endpoint n Status
Address... ...Address Reserved ...Count Reserved Stall Flag
R/W R
0x02n8 0xC000
Device n Endpoint n Count Result Result... ...Result CPU Flags Reserved... ...Reserved
R/W R R/W
0xC002 0xC004 0xC006
Bank Hardware Revision GPIO Control
Address... ...Address Revision... ...Revision Write Protect Enable HSS Enable
R/W R/W
0xC008 0xC00A
CPU Speed Power Control
Reserved... .Reserved Host/Device 2B Wake Enable
0000 0000 0000 1111 0000 0000
HPI Reserved Wake Enable
GPI Reserved Wake Enable
Boost 3V OK
0000 0000
Document #: 38-08015 Rev. *H
Page 92 of 98
CY7C67300
Table 62. Register Summary (continued)
R/W Address Register Bit 15 Bit 7 Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 3 Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Default High Default Low
R/W
0xC00C
Watchdog Timer
Reserved... ...Reserved Timeout Flag Period Select Lock Enable WDT Enable Reset Strobe
0000 0000 0000 0000
R/W
0xC00E
Interrupt Enable
Reserved
OTG Interrupt SPI Interrupt Reserved Enable Enable In Mailbox Interrupt Enable Out Mailbox Interrupt Enable VBUS Pull-up Enable D- Pull-down Reserved Enable Reserved UART Interrupt Enable GPIO Interrupt Enable
Host/Device 2 Host/Device 1 0000 0000 Interrupt Interrupt Enable Enable Timer 1 Interrupt Enable D+ Pull-up Enable ID Status Timer 0 Interrupt Enable D- Pull-up Enable VBUS Valid Flag 0001 0000
HSS Interrupt Enable R/W 0xC098 OTG Control Reserved
Receive Disable
Charge Pump VBUS Enable Discharge Enable OTG Data Status
0000 0000
D+ Pulldown Enable R/W R/W R/W R/W R R/W R/W 0: 0xC010 Timer n 1: 0xC012 0xC014 Breakpoint Count... ...Count Address... ...Address 1: 0xC018 Extended Page n Map 2: 0xC01A 0: 0xC01E GPIO n Output Data 1: 0xC024 0: 0xC020 GPIO n Input Data 1: 0xC026 0: 0xC022 GPIO n Direction 1: 0xC028 0xC038 Upper Address Enable Address... ...Address Data... ...Data Data... ...Data
0000 0xxx 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx
Direction Select... ...Direction Select Reserved Reserved Upper Address Enable Reserved
xxxx 0xxx
R/W
0xC03A
External Memory Control
Reserved XROM Width Select XROM Wait Select Port 2A Diagnostic Enable Pull-down Enable
XRAM XROM XMEM XMEM Merge Enable Merge Enable Width Select Wait Select XRAM XRAM Width Select Wait Select Port 1B Diagnostic Enable LS Pull-up Enable Port 1A Diagnostic Enable FS Pull-up Enable Reserved...
xxxx xxxx xxxx xxxx 0000 0000
R/W
0xC03C
USB Diagnostic
Port 2B Diagnostic Enable ...Reserved
Reserved
Force Select Memory Arbitration Select Monitor Enable
0000 0000 0000 0000
W
0xC03E
Memory Diagnostic
Reserved
Reserved R/W R/W R/W R/W 0xC048 0xC04A 0xC04C 0xC04E IDE Mode IDE Start Address IDE Stop Address IDE Control Reserved... ...Reserved Address... ... Address Address... ...Address Reserved... ...Reserved R/W 0xC050-0 IDE PIO Port xC06E 0xC070 HSS Control HSS Enable RTS Polarity Select CTS Polarity Select XOFF XOFF Enable CTS Enable Receive Interrupt Enable Direction Select IDE Interrupt Enable Done Flag Reserved Mode Select
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
IDE Enable
0000 0000
Done Interrupt Enable
0000 0000
Transmit Done Receive Done One Interrupt Flag Interrupt Flag Stop Bit R/W R/W R/W R/W R/W R/W 0xC072 0xC074 0xC076 0xC078 0xC07A 0xC07C HSS Baud Rate HSS Transmit Gap HSS Data HSS Receive Address HSS Receive Counter HSS Transmit Address Reserved ...Baud Reserved Transmit Gap Select Reserved Data Address... ...Address Reserved ...Counter Address.. ...Address
Transmit Ready HSS Baud...
Packet Mode Receive Receive Pack- Receive Select Overflow Flag et Ready Flag Ready Flag
0000 0000 0000 0000 0001 0111 0000 0000 0000 1001 xxxx xxxx xxxx xxxx 0000 0000 0000 0000
Counter...
0000 0000 0000 0000 0000 0000 0000 0000
Document #: 38-08015 Rev. *H
Page 93 of 98
CY7C67300
Table 62. Register Summary (continued)
R/W Address Register Bit 15 Bit 7 Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 3 Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Default High Default Low
R/W R/W
0xC07E 0xC080 0xC0A0 0xC082 0xC0A2 0xC084 0xC0A4 0xC084 0xC0A4 0xC086 0xC0A6
HSS Transmit Counter Host n Control
Reserved ...Counter Reserved Preamble Enable Sequence Select Sync Enable ISO Enable Reserved
Counter...
0000 0000 0000 0000 0000 0000 Arm Enable 0000 0000 0000 0000 0000 0000
R/W R/W R/W R
Host n Address Host n Count Device n Port Select Host n PID
Address... ...Address Reserved ...Count Reserved ...Reserved Reserved Stall Flag NAK Flag Length Reserved Exception Flag Overflow Flag Sequence Status Underflow Flag Timeout Flag Reserved Error Flag ACK Flag Port Select Reserved... Port Select Reserved Count...
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
W R W R/W
0xC086 0xC0A4 0xC088 0xC0A8 0xC088 0xC0A8 0xC08A 0xC0AA
Host n EP Status Host n Count Result Host n Device Address USB n Control
Reserved PID Select Result... ...Result Reserved... ...Reserved Port B D+ Status Port A Resistors Enable Address Port B D- Status Port B Force D+/State ID Interrupt Enable Reserved Port A D+ Status Port A D- Status Port A Force D State LOB LOA Suspend Enable Mode Select Port B SOF/EOP Enable SOF/EOP Interrupt Enable Port A Connect Change Interrupt Enable Reserved Port B Resistors Enable Port A SOF/EOP Enable Reserved Endpoint Select
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx 0000 0000 0000
R/W
0xC08C
Host 1 Interrupt Enable
VBUS Interrupt Enable
0000 0000
Port B Port A Port B Connect Wake Interrupt Wake Interrupt Change Enable Enable Interrupt Enable R/W 0xC08C Device 1 Interrupt Enable VBUS Interrupt Enable EP7 Interrupt Enable R/W R/W 0xC08E 0xC0AE 0xC090 Device n Address Host 1 Status Reserved... ...Reserved Address VBUS ID Reserved Interrupt Flag Interrupt Flag ID Interrupt Enable EP6 Interrupt Enable Reserved
Done Interrupt Enable Reserved SOF/EOP Interrupt Enable EP1 Interrupt Enable Reset Interrupt Enable EP0 Interrupt Enable
0000 0000
SOF/EOP Timeout Interrupt Enable EP4 Interrupt Enable EP3 Interrupt Enable
0000 0000
EP5 Interrupt Enable
EP2 Interrupt Enable
0000 0000
0000 0000 0000 0000 SOF/EOP Reserved Interrupt Flag Port A SE0 Status Reserved Done Interrupt Flag xxxx xxxx xxxx xxxx
Port B Port A Port B Connect Port A ConPort B Wake Interrupt Wake Interrupt Change nect Change SE0 Flag Flag Interrupt Flag Interrupt Flag Status R/W 0xC090 Device 1 Status VBUS ID Reserved Interrupt Flag Interrupt Flag
SOF/EOP Reset xxxx xxxx Interrupt Flag Interrupt Flag
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 xxxx xxxx Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag R/W R 0xC092 0xC0B2 0xC092 0xC0B2 Host n SOF/EOP Count Device n Frame Number Reserved ...Count SOF/EOP Timeout Flag ...Frame R W R R/W 0xC094 0xC0B4 0xC094 0xC0B4 0xC096 0xC0B6 0xC0AC Host n SOF/EOP Counter Device n SOF/EOP Count Host n Frame Host 2 Interrupt Enable Reserved ...Counter Reserved ...Count Reserved ...Frame Reserved SOF/EOP Interrupt Enable Port A Connect Change Interrupt Enable Reserved Reserved Frame... Count... Counter... SOF/EOP Timeout Interrupt Count Reserved Frame... Count... 0010 1110 1110 0000 0000 0000
0000 0000 xxxx xxxx xxxx xxxx 0010 1110 1110 0000 0000 0000 0000 0000 0000 0000
Port B Port A Port B Connect Wake Interrupt Wake Interrupt Change Enable Enable Interrupt Enable
Done Interrupt Enable
0000 0000
Document #: 38-08015 Rev. *H
Page 94 of 98
CY7C67300
Table 62. Register Summary (continued)
R/W Address Register Bit 15 Bit 7 Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 3 Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Default High Default Low
R/W
0xC0AC
Device 2 Interrupt Enable
Reserved
SOF/EOP Timeout Interrupt Enable EP6 Interrupt Enable EP5 Interrupt Enable EP4 Interrupt Enable EP3 Interrupt Enable
Wake Interrupt Enable EP2 Interrupt Enable
SOF/EOP Interrupt Enable EP1 Interrupt Enable SOF/EOP Interrupt Flag
Reset Interrupt Enable EP0 Interrupt Enable Reserved
0000 0000
EP7 Interrupt Enable R/W 0xC0B0 Host 2 Status Reserved
0000 0000
xxxx xxxx
Port B Port A Port B Wake Interrupt Wake Interrupt Connect Flag Flag Change Interrupt Flag R/W 0xC0B0 Device 2 Status Reserved
Port A Port B Connect SE0 Change Status Interrupt Flag SOF/EOP Timeout Interrupt Enable
Port A SE0 Status Wake Interrupt Flag
Reserved
Done Interrupt Flag Reset Interrupt Flag
xxxx xxxx
SOF/EOP Interrupt Flag
xxxx xxxx
EP7 EP6 EP5 EP4 EP3 EP2 EP1 EP0 xxxx xxxx Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag Interrupt Flag R/W R/W 0xC0C6 0xC0C8 HPI Mailbox SPI Configuration Message... ...Message 3Wire Enable Phase Select SCK Scale Select Polarity Select SS Enable Byte Mode SS Delay Select FullDuplex SS Manual Read Enable Transmit Ready receive Data Ready Reserved 0000 0000 0000 0000 1000 0000 0001 1111 0000 0001 1000 0000 0000 0000 Receive Inter- Transmit Inter- Transfer Inter- 0000 0000 rupt Enable rupt Enable rupt Enable 0000 0000 Reserved Receive Transmit Transfer 0000 0000 Interrupt Flag Interrupt Flag Interrupt Flag 0000 0000 Transmit Transmit 0000 0000 Interrupt Clear Interrupt Clear CRC Enable CRC Clear Receive CRC One in CRC Zero in CRC Reserved... 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 Count... 0000 0000 0000 0000 0000 0000 0000 0000 Count... 0000 0000 0000 0000 0000 0000 Scale Select Baud Select Receive Full UART Enable 0000 0111 0000 0000 Transmit Full 0000 0000 0000 0000 0000 0000 Reserved Prescale Select PWM2 Enable PWM1 Enable Count... Address... Mode Select PWM0 Enable 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Master Master Active Enable Enable R/W 0xC0CA SPI Control SCK Strobe Transmit Empty R/W 0xC0CC SPI Interrupt Enable Reserved... ...Reserved R 0xC0CE SPI Status Reserved... FIFO Error Flag W 0xC0D0 SPI Interrupt Clear Reserved... ...Reserved R/W 0xC0D2 SPI CRC Control CRC Mode ...Reserved R/W R/W R/W R/W R/W R/W R/W R 0xC0D4 0xC0D6 0xC0D8 0xC0DA 0xC0DC 0xC0DE 0xC0E0 0xC0E2 SPI CRC Value SPI Data Port t SPI Transmit Address SPI Transmit Count SPI Receive Address SPI Receive Count UART Control UART Status CRC ...CRC Reserved Data Address... ...Address Reserved ...Count Address... ...Address Reserved ...Count Reserved... ...Reserved Reserved... ...Reserved R/W R/W 0xC0E4 0xC0E6 UART Data PWM Control Reserved Data PWM Enable FIFO Init Receive Full
Transmit Bit Length
Receive Bit Length
PWM3 PWM2 PWM1 PWM0 PWM3 Polarity Select Polarity Select Polarity Select Polarity Select Enable R/W R/W 0xC0E8 PWM Maximum Count Reserved ...Count 0: PWM n Start 0xC0EA 1: 0xC0EE 2: 0xC0F2 3: 0xC0F6 Reserved ...Address
Document #: 38-08015 Rev. *H
Page 95 of 98
CY7C67300
Table 62. Register Summary (continued)
R/W Address Register Bit 15 Bit 7 Bit 14 Bit 6 Bit 13 Bit 5 Bit 12 Bit 4 Bit 11 Bit 3 Bit 10 Bit 2 Bit 9 Bit 1 Bit 8 Bit 0 Default High Default Low
R/W
0: PWM n Stop 0xC0EC 1: 0xC0F0 2: 0xC0F4 3: 0xC0F8 0xC0FA PWM Cycle Count HPI Status Port
Reserved ...Address
Address...
0000 0000 0000 0000
R/W R
Count... ...Count VBUS Flag ID Flag Reserved SOF/EOP2 Flag SIE1msg Reserved Done2 Flag SOF/EOP1 Flag Done1 Flag Reset2 Flag Reset1 Flag Mailbox In Flag Mailbox Out Flag
0000 0000 0000 0000
Resume2 Flag Resume1 Flag SIE2msg
Document #: 38-08015 Rev. *H
Page 96 of 98
CY7C67300
Ordering Information
Table 63. Ordering Information Ordering Code Package Type AEC Pb-Free Temperature Range
CY7C67300-100AXI CY7C67300-100AXA CY7C67300-100AXIT CY7C67300-100AXAT CY3663
100 TQFP 100 TQFP 100 TQFP, tape and reel 100 TQFP, tape and reel Development Kit X X
X X X X
-40 to 85C -40 to 85C -40 to 85C -40 to 85C
Package Diagrams
Figure 92. 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100SA
16.000.25 SQ 14.000.05 SQ 100 76
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH
1
75
3. DIMENSIONS IN MILLIMETERS
0.220.05
0 MIN. STAND-OFF 0.05 MIN. 0.15 MAX.
R 0.08 MIN. 0.20 MAX.
0.25 GAUGE PLANE
R 0.08 MIN. 0.20 MAX. 0.50 TYP.
0-7
DETAIL
A
0.20 MIN. 0.600.15
25
51 1.00 REF. 26 50 NOTE: PKG. CAN HAVE
SEATING PLANE 1.60 MAX.
121 (8X)
OR
1.400.05
TOP LEFT CORNER CHAMFER
4 CORNERS CHAMFER
0.08
0.20 MAX.
51-85048-*C
SEE DETAIL
A
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. EZ-Host is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-08015 Rev. *H
Page 97 of 98
(c) Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C67300
Document History Page
Document Title: EZ-HostTM Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support Document Number: 38-08015 REV. ECN NO. Issue Date Orig. of Change Description of Change
** *A *B
111872 116989 125262
03/22/02 08/23/02 04/10/03
MUL MUL MUL
New Data Sheet Preliminary Data Sheet Added Memory Map Section and Ordering Information Section Moved Functional Register Map Tables into Register section General Clean-up Added Interface Description Section and Power Savings and Reset Section Added Char Data General Clean-up Corrected font to enable correct symbol display Final Data Sheet Changed Memory Map Section and added CLKSEL to Pin Description Added USB OTG Logo General Clean-up Title changed indicating AEC Grade Added information for AEC qualified including part number Fixed misc. errors including: Table 4-1: UART does not have alternate location Section 4.3.4 had incorrect register address Table 4-10 had incorrect pin definitions Section 4.16.2 changed GPIO[31:20] to GPIO[31:30] Corrected Table 7-6 and 7-14
*C
126210
05/23/03
MUL
*D *E
127335 129395
05/29/03 10/01/03
KKV MUL
*F
443992
See ECN
VCS
*G *H
566465 1063560
See ECN See ECN
KKVTMP Added the lead free information on the Ordering Information Section. Implemented the new template with no numbers on the headings. ARI Changed Ordering Informatijon table to reflect Automotive Qualification and to meet the MPN Part Number changes reflected in ECN 884880. Changed the EZ-Host Pin Diagram figure to reflect the pin changes. Edited.
Document #: 38-08015 Rev. *H
Page 98 of 98

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